1.8 LPDDR, DDR2, and DDR3

DDRIO is a multi-standard I/O buffer optimized for LPDDR, DDR2, and DDR3 performance. SmartFusion2/IGLOO2 devices include two DDR subsystems: the fabric DDR controllers (FDDR) and microcontroller subsystem (MSS) DDR (MDDR) controllers. All DDRIO can be configured as differential I/O or two single-ended I/O. DDRIO can be connected to the respective DDR sub-system PHYs or can be used as user I/O.

For more information on FDDR and MDDR, see the SmartFusion2 FPGA Fabric DDR Controller Configuration Guide and SmartFusion2 MSS DDR Controller Configuration Guide

The following table lists the differences between LPDDR, DDR2, and DDR3.

Table 1-16. LPDDR/DDR2/DDR3 Parameters

Parameter

LPDDR

DDR2

DDR3

VDDQ

1.8 V

1.8 V

1.5 V

VTT, VREF

—

0.9 V

0.75 V

Clock, address, and command (CAC) layout

Asymmetrical tree branch

Symmetrical tree branch

Daisy chained (fly-by)

Data strobe

Single-ended

Differential

Differential

ODT

None

Static

Dynamic

Match Addr/CMD/Ctrl to clock tightly

Yes

Yes

Yes

Match DQ/DM/DQS tightly

Yes

Yes

Yes

Match DQS to clock loosely

Yes

Yes

Not required

Interface

LVCMOS_18 or SSTL18 for LPDDR1

SSTL_18

SSTL_15

Impedance Calibration

LVCMOS18 - Not required SSTL18 - Required

150_1%

240_1%

A major difference between DDR2 and DDR3 SDRAM is the use of data leveling. To improve signal integrity and support higher frequency operations, a fly-by termination scheme is used with the clocks, command, and address bus signals. Fly-by termination reduces simultaneous switching noise by deliberately causing flight-time skew between the data strobes at every DDR3 chip. Fly-by termination requires controllers to compensate for this skew by adjusting the timing per byte lane. To obtain length matching, short TMATCH_OUT to TMATCH_IN with the shortest loop.

For more information about DDR memories, see the following documents:

  • JESD209B-JEDEC STANDARD—Low Power Double Data Rate (LPDDR) SDRAM Standard

  • JESD79-2F-JEDEC STANDARD—DDR2 SDRAM Specification

  • JESD79-3F-JEDEC STANDARD—DDR3 SDRAM Standard