67.4.2.5 Low-power Mode Summary Table

The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake-up sources can be configured individually. The table below gives a summary of the low-power mode configurations.

Table 67-12. Low-power Mode Configuration Summary
SubmodeLow-power Mode
BackupUltra-low-powerIdle
–Self-refreshULP0ULP1
64 kHz RC Oscillator, 32 kHz Oscillator, RTC, Backup Memory and Registers, PORON
12 MHz RC OscillatorOFFON
VDDCORE RegulatorOFFON
CoreOFF (not powered)Powered (not clocked)
Memory, PeripheralsOFF (not powered)Powered (512 Hz)Powered 
(not clocked)Powered (clocked)
Mode EntrySHDWC, FLEXCOM, Asynchronous Partial Wake-UpDDR in Self-refresh,SHDWCDDR in Self-refresh, Frequency reduced in PMC, WFIDDR in Self-refresh, CKGR_MOR.WAIT-MODE=1DDR in Self-refresh, WFI
Potential Wake-up SourcesRefer tp Backup ModeBackup mode sourcesAny interruptRefer to ULP1 ModeAny interrupt
Core at Wake-upResetClocked back at 512 HzClocked back at 12 MHzClocked back at full speed
PIO State While in Low-power ModeResetPrevious state saved
PIO State at Wake-upInputs with pull-upsUnchanged
Consumption(2)IVDDBU= 4.5 μA typ(3)
at 25°C/3.0VIVDDBU= 4.5 μA typ(3)
at 25°C/3.0V

IVDDIODDR = 40 μA

0.21 mA at 25°C/1.1V

0.27 mA at 25°C/1.2V

0.17 mA at 25°C/1.1V

0.27 mA at 25°C/1.2V

28 mA at 25°C/1.2V(4)
Wake-up Time(1)Start-up timeStart-up time300 ms 15 μs800 ns at 498 MHz
Note:
  1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the main oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up time is defined as the time taken for wake-up until the first instruction is fetched.
  2. The external loads on PIOs are not taken into account in the calculation.
  3. Total current consumption.
  4. Dynamic Clock Gating enabled (L2CC_POWCR.DCKGATEN = 1).