67.4.1.1 Active Mode Power Consumption Versus Modes

The power consumption values are measured under the following operating conditions:

  • Parts are from typical process
  • VDDIOPx = 3.3V
  • VDDSDMMC0 and VDDSDMMC1 = 1.8V to 3.3V (high frequency)
  • VDDCORE = 1.2V ± -2%
  • VDDBU = 1.6V to 3.6V
  • TA = as specified in tables "Typical Peripheral Power Consumption by Peripheral in Active Mode" and "Power Consumption in Active Mode: AMP2"
  • There is no consumption on the device I/Os.
  • All peripheral clocks are disabled.
Figure 67-1. Measurement Schematics
Table 67-10. Typical Peripheral Power Consumption by Peripheral in Active ModeMeasurements made at TA = 25°C and with peripheral clock enabled.
Peripheral Clock Consumption on VDDCORE Conditions Consumption (typ) Unit
GMAC MCK/2 – See Note 1. 12 *MCK + 1840*DR (Data rate in Mbits/s) µA
XDMAC0 MCK – See Note 2. 17.6 * MCK + 4.92 * DR (MCK in MHz, Data rate in Mbytes/s)
XDMAC1 MCK –
ICM MCK/2 3.52 – – µA/MHz
AES MCK 8.79
AESB MCK 7.49
TDES MCK/2 0.85
SHA MCK 3.88
MPDDRC MCK 45.21 See Note 3. 67 * MCK + 3.11 * DR + 1609 (MCK in MHz, Data rate in Mbytes/s) µA
HSMC MCK/2 20.12 – – µA/MHz
PIOA MCK/2 11.39
FLEXCOM0 MCK/2 -
FLEX0_USART 5.21
FLEX0_SPI 7.39
FLEX0_TWI 3.88
FLEXCOM1 MCK/2 See FLEXCOM0
FLEXCOM2 MCK/2 See FLEXCOM0
FLEXCOM3 MCK/2 See FLEXCOM0
FLEXCOM4 MCK/2 See FLEXCOM0
UART0 MCK/2 1.09
UART1 MCK/2 0.97
UART2 MCK/2 1.21
UART3 MCK/2 0.85
UART4 MCK/2 0.85
TWIHS0 MCK/2 3.27
TWIHS1 MCK/2 3.39
SDMMC0 MCK 8.61
SDMMC1 MCK 8.61
SPI0 MCK/2 4.61
SPI1 MCK/2 4.48
TC0 MCK/2 3.03
TC1 MCK/2 4
PWM MCK/2 7.03
ADC MCK/2 2.3
UHPHS MCK/2 – See Note 4. 12 *MCK + 490*DR (MCK in MHz, Data rate in Mbytes/s) µA
UDPHS MCK/2 See Note 5. 10 *MCK + 206*DR (MCK in MHz, Data rate in Mbytes/s)
SSC0 MCK/2 1.58 – – µA/MHz
SSC1 MCK/2 1.58
LCDC MCK – See Note 6. 9.8 *MCK + 32 *Pix_CLK + 15.7*DR_Baselayer +30.1*DR_Overlayer (MCK & Pixelclock in MHz, Data rate in Mbytes/s); µA
ISC MCK See Note 7. 10.9*MCK + 22.4*ISPCK + 12.38*DR_sensor (MCK & ISPCK in MHz, Data rate in Mbytes/s)
TRNG MCK/2 760 – –
PDMIC MCK/2 8.24 – – µA/MHz
QSPI0 MCK 1.94
QSPI1 MCK 1.94
I2SC0 MCK/2 0.61
I2SC1 MCK/2 0.61
CAN0 MCK/2 9.7
CAN1 MCK/2 7.27
Note:
  1. In Linux OS, use the ‘iperf’ command to perform bidirectional data transfers. Measure GMAC consumption at different transfer speeds.
  2. XDMAC is initialized and one channel performs a memory-to-memory transfer. During test, the data rate is adjusted by changing the DMA setting and the burst size.
  3. DDR3 devices are initialized (fully functional). XDMAC performs a memory-to-memory transfer inside the DDR area. Total consumption of MPDDRC and XDMAC is measured. MPDDRC consumption is calculated by discounting XDMAC consumption.
  4. In Linux OS, measure UHPHS consumption at different transfer speeds.
  5. In Linux OS, build a mass storage using UDPHS. Measure UDPHS consumption at different transfer speeds.
  6. The LCD timing engine and each display layer are switched on in sequence. The static image (using random data) is displayed under various resolutions. The 24-bpp RGB888 color space is set for all layers. Auxiliary functions such as rotation, scaling, color space conversion, color look-up table, and chroma upsampling are disabled.
  7. ISC performs image sensor preview.

In order to maximize performance, each Peripheral Clock has been timed to H32MX clock frequency. The peripheral frequency can be reduced with the help of a divider in PMC_PCR.

Table 67-11. Power Consumption in Active Mode: AMP2
Conditions TA = 25°C Consumption
Dhrystone (mA) CoreMark (mA)
PLL clock is 1000 MHz, Arm Core clock is 500 MHz, MCK is 166 MHz.

– Caches L1 and L2 enabled

– Code running off of internal SRAM

– Code speed optimization

– Run Dhrystone / CoreMark benchmark

– Peripheral clock disabled

MRL C

MRL B

 114.4 108.8
MRL A 237.2 233.7