15.5.4 L2CC Auxiliary Control Register

The L2 Cache Controller (L2CC) must be disabled in the L2CC Control Register prior to any write access to this register.

Name: L2CC_ACR
Offset: 0x104
Reset: 0x02020000
Property: Read/Write in Secure mode, Read-only in Non-secure mode

Bit 3130292827262524 
   IPENDPENNSIACNSLENCRPOLFWA[1] 
Access  
Reset 000010 
Bit 2322212019181716 
 FWA[0]SAOENPENEMBENWAYSIZE[2:0]ASS 
Access  
Reset 00000010 
Bit 15141312111098 
   SAIEEXCCSBDLEHPSO   
Access  
Reset 0000 
Bit 76543210 
          
Access  
Reset  

Bit 29 – IPEN Instruction Prefetch Enable

ValueDescription
0

Instruction prefetching is disabled. This is the default value.
1

Instruction prefetching is enabled.

Bit 28 – DPEN Data Prefetch Enable

ValueDescription
0

Data prefetching is disabled. This is the default value.
1

Data prefetching is enabled.

Bit 27 – NSIAC Non-Secure Interrupt Access Control

ValueDescription
0

Interrupt Clear Register and Interrupt Mask Register can only be modified or read with secure accesses. This is the default value.
1

Interrupt Clear Register and Interrupt Mask Register can be modified or read with secure or non-secure accesses.

Bit 26 – NSLEN Non-Secure Lockdown Enable

ValueDescription
0

Lockdown registers cannot be modified using non-secure accesses. This is the default value.
1

Non-secure accesses can write to the lockdown registers.

Bit 25 – CRPOL Cache Replacement Policy

ValueDescription
0

Pseudo-random replacement using the LFSR algorithm.
1

Round-robin replacement. This is always the default value.

Bits 24:23 – FWA[1:0] Force Write Allocate

ValueDescription
0

The L2 Cache controller uses AWCACHE attributes for WA. This is the default value.
1

User forces no allocate, WA bit must be set to 0.
2

User overrides AWCACHE attributes, WA bit must be set to 1. All cacheable write misses become write allocated.
3

The write allocation is internally mapped to 00.

Bit 22 – SAOEN Shared Attribute Override Enable

ValueDescription
0

Treats shared accesses. This is the default value.
1

Shared attribute is internally ignored.

Bit 21 – PEN Parity Enable

ValueDescription
0

Disabled. This is the default value.
1

Enabled.

Bit 20 – EMBEN Event Monitor Bus Enable

ValueDescription
0

Disabled. This is the default value.
1

Enabled.

Bits 19:17 – WAYSIZE[2:0] Way Size

ValueNameDescription
0x0 RESERVED

Reserved
0x1 16KB_WAY

16-Kbyte way set associative
0x2 RESERVED

Reserved
0x3 RESERVED

Reserved
0x4 RESERVED

Reserved
0x5 RESERVED

Reserved
0x6 RESERVED

Reserved
0x7 RESERVED

Reserved

Bit 16 – ASS Associativity

ValueDescription
0

8-way.This is the default value.
1

Reserved.

Bit 13 – SAIE Shared Attribute Invalidate Enable

ValueDescription
0

Shared invalidate behavior is disabled. This is the default value.
1

Shared invalidate behavior is enabled if the Shared Attribute Override Enable bit is not set.

Shared invalidate behavior is enabled if both:

  • Shareable Attribute Invalidate Enable bit is set in the Auxiliary Control Register, bit[13]
  • Shared Attribute Override Enable bit is not set in the Auxiliary Control Register, bit[22]

Bit 12 – EXCC Exclusive Cache Configuration

ValueDescription
0

Disabled. This is the default value.
1

Enabled.

Bit 11 – SBDLE Store Buffer Device Limitation Enable

ValueDescription
0

Store buffer device limitation is disabled. Device writes can take all slots in the store buffer. This is the default value.
1

Store buffer device limitation is enabled.

Bit 10 – HPSO High Priority for SO and Dev Reads Enable

ValueDescription
0

Strongly Ordered and Device reads have lower priority than cacheable accesses when arbitrated in the L2CC host ports. This is the default value.
1

Strongly Ordered and Device reads get the highest priority when arbitrated in the L2CC host ports.