56.7.40 PWM Channel Mode Register
This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.
| Name: | PWM_CMRx |
| Offset: | 0x0200 + x*0x20 [x=0..3] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PPM | DTLI | DTHI | DTE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TCTS | DPOLI | UPDS | CES | CPOL | CALG | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CPRE[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 19 – PPM Push-Pull Mode
The Push-Pull mode is enabled for channel x.
| Value | Description |
|---|---|
| 0 |
The Push-Pull mode is disabled for channel x. |
| 1 | The Push-Pull mode is enabled for channel x. |
Bit 18 – DTLI Dead-Time PWMLx Output Inverted
| Value | Description |
|---|---|
| 0 |
The dead-time PWMLx output is not inverted. |
| 1 |
The dead-time PWMLx output is inverted. |
Bit 17 – DTHI Dead-Time PWMHx Output Inverted
| Value | Description |
|---|---|
| 0 |
The dead-time PWMHx output is not inverted. |
| 1 |
The dead-time PWMHx output is inverted. |
Bit 16 – DTE Dead-Time Generator Enable
| Value | Description |
|---|---|
| 0 |
The dead-time generator is disabled. |
| 1 |
The dead-time generator is enabled. |
Bit 13 – TCTS Timer Counter Trigger Selection
| Value | Description |
|---|---|
| 0 |
The comparator of the channel x (OCx) is used as the trigger source for the Timer Counter (TC). |
| 1 |
The counter events of the channel x is used as the trigger source for the Timer Counter (TC). |
Bit 12 – DPOLI Disabled Polarity Inverted
| Value | Description |
|---|---|
| 0 |
When the PWM channel x is disabled (CHIDx(PWM_SR) = 0), the OCx output waveform is the same as the one defined by the CPOL bit. |
| 1 |
When the PWM channel x is disabled (CHIDx(PWM_SR) = 0), the OCx output waveform is inverted compared to the one defined by the CPOL bit. |
Bit 11 – UPDS Update Selection
If the PWM period is center-aligned (CALG=1):
0: The update occurs at the next end of the PWM period after writing the update register(s).
1: The update occurs at the next end of the PWM half period after writing the update register(s).
If the PWM period is left-aligned (CALG=0), the update always occurs at the end of the PWM period after writing the update register(s).
Bit 10 – CES Counter Event Selection
If the PWM period is center-aligned (CALG=1):
0: The channel counter event occurs at the end of the PWM period.
1: The channel counter event occurs at the end of the PWM period and at half the PWM period.
If the PWM period is left-aligned (CALG=0), the channel counter event occurs at the end of the period and the CES bit has no effect.
Bit 9 – CPOL Channel Polarity
| Value | Description |
|---|---|
| 0 |
The OCx output waveform (output from the comparator) starts at a low level. |
| 1 |
The OCx output waveform (output from the comparator) starts at a high level. |
Bit 8 – CALG Channel Alignment
| Value | Description |
|---|---|
| 0 |
The period is left-aligned. |
| 1 |
The period is center-aligned. |
Bits 3:0 – CPRE[3:0] Channel Prescaler
| Value | Name | Description |
|---|---|---|
| 0 | MCK |
Peripheral clock |
| 1 | MCK_DIV_2 |
Peripheral clock/2 |
| 2 | MCK_DIV_4 |
Peripheral clock/4 |
| 3 | MCK_DIV_8 |
Peripheral clock/8 |
| 4 | MCK_DIV_16 |
Peripheral clock/16 |
| 5 | MCK_DIV_32 |
Peripheral clock/32 |
| 6 | MCK_DIV_64 |
Peripheral clock/64 |
| 7 | MCK_DIV_128 |
Peripheral clock/128 |
| 8 | MCK_DIV_256 |
Peripheral clock/256 |
| 9 | MCK_DIV_512 |
Peripheral clock/512 |
| 10 | MCK_DIV_1024 |
Peripheral clock/1024 |
| 11 | CLKA |
Clock A |
| 12 | CLKB |
Clock B |