55.7.2 PDMIC Mode Register
This register can only be written if the WPEN bit is cleared in the PDMIC Write Protection Mode Register.
| Name: | PDMIC_MR |
| Offset: | 0x04 |
| Reset: | 0x00F00000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PRESCAL[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKS | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bits 14:8 – PRESCAL[6:0] Prescaler Rate Selection
PRESCAL determines the frequency of the PDM bitstream sampling clock (PDMIC_CLK):
where SELCK is either fperipheral clock or fGCLK clock depending on the value of bit CLKS (fperipheral clock or fGCLK clock is the clock frequency in Hz).
Bit 4 – CLKS Clock Source Selection
| Value | Description |
|---|---|
| 0 | Peripheral clock selected |
| 1 | GCLK clock selected (This clock source can be independent of the processor clock.) |