Introduction

Microchip PolarFire® FPGAs support 1G Ethernet solutions for various networking applications. In PolarFire devices, 10/100/1000 Mbps (1G) Ethernet is implemented using the CoreTSE_AHB Media Access Control (MAC) soft IP core. The CoreTSE_AHB IP implements a Serial Gigabit Media-Independent Interface (SGMII or GMII) with an Ethernet PHY. This Ethernet interface can be implemented in the FPGA by using either a transceiver (PF_XCVR IP) or a GPIO with clock and data recovery (PF_IOD_CDR IP) capability. In this demo, the 1G Ethernet solution is implemented in the FPGA design by using GPIOs with CDR capability and CoreTSE_AHB IP.

The CoreTSE_AHB IP core enables system designers to implement a broad range of Ethernet designs, from low cost 10/100 Ethernet to higher performance 1 Gigabit ports. The CoreTSE_AHB IP core is suitable for use in networking equipment such as switches, routers, and data acquisition systems.

The CoreTSE_AHB IP has the following major interfaces:

  • 10/100/1000 Mbps Ethernet MAC with a Gigabit Media Independent Interface (GMII) and Ten Bit Interface (TBI) to support Serial Gigabit Media Independent Interface (SGMII), 1000BASE-T, and 1000BASE-X.
  • GMII or TBI physical layer interface that connects to the Ethernet PHY
  • MAC data path interface

The CoreTSE_AHB IP core is available in two different versions:

  • CoreTSE_AHB: Uses AHB interface for both the transmit and receive paths.
  • CoreTSE_AHB (Non-AMBA): Uses direct access to MAC with a streaming packet interface.

For more information about CoreTSE_AHB IP, see the CoreTSE AHB Handbook .

CoreTSE_AHB IP core requires license for using in Libero® SoC design. For license request, contact Microchip Technical Support.

This demo design implements a webserver application and a Trivial File Transfer Protocol (TFTP) server using the PolarFire Evaluation Kit board. For more information about this board, see UG0747: PolarFire FPGA Evaluation Kit User Guide .

This demo design demonstrates the following:

  • Use of Ethernet MAC connected to a SGMII PHY.
  • Integration of the CoreTSE_AHB MAC driver with the lwIP TCP/IP stack and FreeRTOS operating system.
  • Implementation of webserver on the PolarFire Evaluation board.
  • Implementation of the TFTP server on the PolarFire Evaluation board.
  • Procedure to run webserver and the TFTP server designs on the PolarFire Evaluation board.

This demo design can be programmed using either of the following options: