2 Demo Design

The following is the data flow of the demo design:

  1. PF_CCC_0 provides the clock to the Mi-V processor and other APB peripherals.
  2. PF_IOD_CDR_CCC drives the IOD CDR clocks PF_IOD_CDR: TX_CLK_G and HS_IO_CLK.
  3. Mi-V performs the following functions:
    • Executes the application from LSRAM (PF_SRAM IP)
    • Configures the ZL30364 clock generation hardware through CoreSPI IP to generate reference clocks for the VSC PHY and the IOD CDR fabric module.
    • Configures the CoreTSE_AHB IP MAC in TBI mode and initializes the MAC in 1000 Base-T.
    • Sends a request to the CoreTSE_AHB IP to negotiate with the on-board VSC8575 PHY.

  4. CoreTSE_AHB IP implements the 1G Ethernet MAC and is configured to interface with the PF_IOD_CDR block in the SGMII mode. The CoreTSE IP has an inbuilt Management Data Input/Output (MDIO) interface to exchange control and status information with the VSC PHY.

  5. PF_IOD_CDR IP performs the following functions:
    • Interfaces with the on-board VSC8575 PHY.
    • Recovers the data and clock from the incoming RX_P and RX_N ports. Deserializes the recovered data and sends 10-bit parallel data to the CoreTSE.
    • Receives Ethernet data from the VSC PHY through the RX_P and RX_N input pads, gears down the receive data rate, and deserializes the data.
  6. The deserialized data is sent from SGMII_CDR_0:RX_DATA[9:0] to CoreTSE_AHB IP: RCG[9:0]. The CoreTSE_AHB IP MAC receives the Ethernet packet from the on-board Ethernet PHY through 
high-speed PF_IOD_CDR IP using the built-in DMA controller and Mi-V processes the Ethernet packets.
  7. The Ethernet packets from the Mi-V processor are sent to CoreTSE_AHB IP, and CoreTSE_AHB IP:TCG[9:0] is sent to SGMII_CDR_0:TX_DATA[9:0].
  8. PF_IOD_CDR serializes the data, gears up the transmit data rate, and transmits the data to the on-board VSC PHY through the TX_P and TX_N output pads.

The following are the demo design features:

  • Webserver
  • In-application programming (IAP) using TFTP server

The following figure shows the high-level demo design block diagram. In this demo design, CoreTSE_AHB IP is instantiated in the FPGA fabric and connected to the on-board VSC PHY using IOD CDR IP.

Figure 2-1. Demo Design High-level Block Diagram