12 Revision History

The following is the list of changes in revision C of the document:

• Updated Figure 2-2, Figure 2-3, Figure 2-4, Figure 2-5, Figure 2-6, Figure 2-8, Figure 2-9, Figure 2-10, and Figure 2-11.
• Removed Design Memory Map section.
• Updated directory file location in SoftConsole Firmware Project.
• Updated Figure 5-1 and Figure 5-2.
• Updated directory file location in Configure Design Initialization Data and Memories.
• Updated directory file location in Appendix 2: Running the SoftConsole Project in Debug Mode from LSRAM or DDR Memory.
• Updated directory file location in Appendix 3: Programming the Device and External SPI FlashPro Express.
• Updated Tcl_scripts directory location in Appendix 4: Running the TCL Script.

The following is the list of changes in revision B of the document:

• Removed hyperlink in Application Layer.
• Updated demo design files link in Demo Prerequisites.
• Updated directory file location in SoftConsole Firmware Project.
• Updated webserver hex file location in Configure Design Initialization Data and Memories.
• Updated browse folder location in Running TFTP Demo.
• Updated SoftConsole project location in Appendix 2: Running the SoftConsole Project in Debug Mode from LSRAM or DDR Memory.
• Updated .job file location in Appendix 3: Programming the Device and External SPI FlashPro Express.
• Updated Tcl_scripts directory location in Appendix 4: Running the TCL Script.

The following is the list of changes in revision A of the document:

• The document was migrated to the Microchip template.
• The document number was updated to DS00004569A from 50200834.
• Updated the Table 3-1.
• Updated the section Demo Design.
• Updated the Figure 2-2.
• Updated the section Mi-V Soft Processor.
• Updated the section PF_SRAM_AHBL_AXI.
• Updated the Figure 2-7, Figure 2-8, Figure 2-9, and Figure 2-10.
• Updated the Figure 2-11.
• Updated the section PF_CCC_0.
• Updated the section PF_IOD_CDR_CCC.
• Updated the section CORESPI_0.
• Updated the section CoreAPB3_0.
• Updated the section Clocking Structure.
• Updated the section Configure Design Initialization Data and Memories.
• Updated the section Appendix 2: Running the SoftConsole Project in Debug Mode from LSRAM or DDR Memory.

Added Appendix 4: Running the TCL Script.

The following is a summary of the changes made in this revision.

• Updated the document for Libero® SoC v12.2.
• Removed the references to Libero version numbers.

The document was updated for Libero SoC v12.0 release.