| 116 | PIOBU0 | VBAT | I/O | Tamper I/Os | – |
| 115 | PIOBU1 | VBAT | I/O | Tamper I/Os | – |
| 117 | PIOBU2 | VBAT | I/O | Tamper I/Os | – |
| 118 | PIOBU3 | VBAT | I/O | Tamper I/Os | – |
| 79 | HHSA_CC1 | VDD_3V3 | I/O | Pins to identify the USBA male side | – |
| 82 | HHSA_CC2 | VDD_3V3 | I/O | Pins to identify the USBA male side | – |
| 80 | HHSA_DM | VDD_3V3 | I/O | USB host/device port A high speed data - | – |
| 81 | HHSA_DP | VDD_3V3 | I/O | USB host/device port A high speed data + | – |
| 74 | HHSB_CC1 | VDD_3V3 | I/O | Pins to identify the USBB male side | – |
| 77 | HHSB_CC2 | VDD_3V3 | I/O | Pins to identify the USBB male side | – |
| 75 | HHSB_DM | VDD_3V3 | I/O | USB host/device port B high speed data - | – |
| 76 | HHSB_DP | VDD_3V3 | I/O | USB host/device port B high speed data + | – |
| 71 | HHSC_DM | VDD_3V3 | I/O | USB host port C high speed data - | – |
| 72 | HHSC_DP | VDD_3V3 | I/O | USB host port C high speed data + | – |
| 164 | MIPI_CK_N | VDDOUT25 | I | MIPI DPHY differential input clock lane - | – |
| 163 | MIPI_CK_P | VDDOUT25 | I | MIPI DPHY differential input clock lane + | – |
| 168 | MIPI_D0_N | VDDOUT25 | I | MIPI DPHY differential input data lane 0 - | – |
| 166 | MIPI_D1_N | VDDOUT25 | I | MIPI DPHY differential input data lane 1 - | – |
| 167 | MIPI_D0_P | VDDOUT25 | I | MIPI DPHY differential input data lane 0 + | – |
| 165 | MIPI_D1_P | VDDOUT25 | I | MIPI DPHY differential input data lane 1 + | – |
| 105 | NRST | VDD_3V3 | I/O, PU | External nReset input/output | Low |
| 104 | NRST_OUT | VDD_3V3 | O | Microprocessor reset output | Low |
| 146 | SHDN | VBAT | O | Shutdown control | – |
| 134 | WKUP0 | VBAT | I | Wake-up input | – |
| 113 | AUDIOCLK | VDD_3V3 | O | Audio clock output | – |
| 114 | JTAGSEL | VBAT | I, PD | JTAG selection | High |
| 14 | MCP16502_HPM | 5V_MAIN | I | High Performance mode input pin. In combination with
PWRHLD and LPM, this pin defines the MCP16502 power mode status. Connect
to ground if not used. | High |
| 15 | NSTART_SOM | 5V_MAIN | I, PU | Start Event input. Drive nSTRT to low to initiate a
start-up sequence. nSTRT is pulled up internally. A capacitor can be
connected to nSTRT to automatically initiate a power-up sequence when
the main supply rises. | Low |
| 8 | SEL_VLDO1 | 5V_MAIN | I | LDO1 Default Output Voltage Selection pin.
Three-state input | – |
| 98 | 24M_EN | VDD_3V3 | I | 24-MHz MEMS oscillator input pin used for the main
clock | High |
| 38 | NAND_CS_IN | VDD_3V3 | I, PU | NAND Flash chip select input. Connect to
pin 39. | Low |
| 69 | QSPI1_CS_IN | VDD_3V3 | I, PU | QSPI NOR Flash chip select input. Connect to
pin 68. | Low |
