15.13.2 SERCOM in SPI Mode in PL0

Table 15-50. SPI Timing Characteristics and Requirements(1)
SymbolParameterConditionsMin.Typ.Max.Units
tSCKSCK periodMaster, VDD>2.70V141153 ns
Master, VDD>1.8V147159
tSCKWSCK high/low widthMaster-0.5*tSCK-
tSCKRSCK rise time(2)Master-0.25*tSCK-
tSCKFSCK fall time(2)Master-0.25*tSCK-
tMISMISO setup to SCKMaster, VDD>2.70V141
Master, VDD>1.8V147
tMIHMISO hold after SCKMaster, VDD>2.70V0
Master, VDD>1.8V0
tMOSMOSI setup SCKMaster, VDD>2.70V 30
Master, VDD>1.8V 30.6
tMOHMOSI hold after SCKMaster, VDD>2.70V-9
Master, VDD>1.8V-8.5
tSSCKSlave SCK PeriodSlave, VDD>2.70V220250
Slave, VDD>1.8V230250-
tSSCKWSCK high/low widthSlave-0.5*tSCK-
tSSCKRSCK rise time(2)Slave-0.25*tSCK-
tSSCKFSCK fall time(2)Slave-0.25*tSCK-
tSISMOSI setup to SCKSlave, VDD>2.70V42--
Slave, VDD>1.8V42
tSIHMOSI hold after SCKSlave, VDD>2.70V0
Slave, VDD>1.8V0
tSSS SS setup to SCK SlavePRELOADEN=1
PRELOADEN=0
tSSHSS hold after SCKSlave
tSOSMISO setup before SCKSlave, VDD>2.70V 109
Slave, VDD>1.8V 115
tSOHMISO hold after SCKSlave, VDD>2.70V17.3
Slave, VDD>1.8V17.3
tSOSSMISO setup after SS lowSlave, VDD>2.70V 95
Slave, VDD>1.8V 102
tSOSHMISO hold after SS highSlave, VDD>2.70V10.2 ns
Slave, VDD>1.8V10.2
Note: 1. These values are based on simulation. They are not covered by production test limits or characterization.
Figure 15-5. SPI Timing Requirements in Master Mode
Figure 15-6. SPI Timing Requirements in Slave Mode
Maximum SPI Frequency
  • Master Mode

    fSCKmax = 1/2*(tMIS + tvalid), where tvalid is the slave time response to output data after detecting an SCK edge. For a non-volatile memory with tvalid = 12ns Max, fSPCKMax = 3.7MHz @ VDDIO > 2.7V

  • Slave Mode

    fSCKmax = 1/2*(tSOV + tsu), where tsu is the setup time from the master before sampling data. With a perfect master (tsu=0), fSPCKMax = 6MHz @ VDDIO > 2.7V