15.13.3 SERCOM in SPI Mode in PL2

Table 15-51. SPI Timing Characteristics and Requirements(1)
SymbolParameterConditions Min.Typ.Max.Units
tSCKSCK periodMaster, VDD>2.70V41.153 ns
Master, VDD>1.8V52.665
tSCKWSCK high/low widthMaster-0.5*tSCK-
tSCKRSCK rise time(2)Master-0.25*tSCK-
tSCKFSCK fall time(2)Master-0.25*tSCK-
tMISMISO setup to SCKMaster, VDD>2.70V41.1
Master, VDD>1.8V52.6
tMIHMISO hold after SCKMaster, VDD>2.70V0
Master, VDD>1.8V0
tMOSMOSI setup SCKMaster, VDD>2.70V 8.5
Master, VDD>1.8V 13.1
tMOHMOSI hold after SCKMaster, VDD>2.70V0.5
Master, VDD>1.8V1
tSSCKSlave SCK PeriodSlave, VDD>2.70V7490-
Slave, VDD>1.8V95110-
tSSCKWSCK high/low widthSlave-0.5*tSCK-
tSSCKRSCK rise time(2)Slave-0.25*tSCK-
tSSCKFSCK fall time(2)Slave-0.25*tSCK-
tSISMOSI setup to SCKSlave, VDD>2.70V10.3--
Slave, VDD>1.8V11.8--
tSIHMOSI hold after SCKSlave, VDD>2.70V0--
Slave, VDD>1.8V0--
tSSSSS setup to SCKSlavePRELOADEN=1
PRELOADEN=0
tSSHSS hold after SCKSlave
tSOSMISO setup before SCKSlave, VDD>2.70V--36.9ns
Slave, VDD>1.8V--47.5
tSOHMISO hold after SCKSlave, VDD>2.70V11.5--
Slave, VDD>1.8V11.5--
tSOSSMISO setup after SS lowSlave, VDD>2.70V--31
Slave, VDD>1.8V--41.3
tSOSHMISO hold after SS highSlave, VDD>2.70V6.2--
Slave, VDD>1.8V6.2--
Note: 1. These values are based on simulation. They are not covered by production test limits or characterization.
Figure 15-7. SPI Timing Requirements in Master Mode
Figure 15-8. SPI Timing Requirements in Slave Mode
Maximum SPI Frequency
  • Master Mode

    fSCKmax = 1/2*(tMIS + tvalid), where tvalid is the slave time response to output data after detecting an SCK edge. For a non-volatile memory with tvalid = 12ns Max, fSPCKMax = 9.8MHz @ VDDIO > 2.7V

  • Slave Mode

    fSCKmax = 1/2*(tSOV + tsu), where tsu is the setup time from the master before sampling data. With a perfect master (tsu=0), fSPCKMax = 16.3MHz @ VDDIO > 2.7V