14.2.1.4.1 Power-on Procedure

The power-on procedure to P_ON state is shown in the figure below.

Figure 14-21. Power-on Procedure to P_ON State

When the external supply voltage (V_DD) is initially supplied to the AT86RF212B, the radio transceiver enables the crystal oscillator (XOSC) and the internal 1.8V voltage regulator for the digital domain (DVREG). After t_TR1 = 420µs (typ.), the master clock signal is available at pin 17 (CLKM) at default rate of 1MHz. As soon as CLKM is available the SPI is enabled and can be used to control the transceiver. As long as no state change towards state TRX_OFF is performed, the radio transceiver remains in P_ON state.