18.6.23 RTC Tamper Mode Register
| Name: | RTC_TMR |
| Offset: | 0x58 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TRLOCK | |||||||||
| Access | W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| POL7 | POL6 | POL5 | POL4 | POL3 | POL2 | POL1 | POL0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN7 | EN6 | EN5 | EN4 | EN3 | EN2 | EN1 | EN0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – TRLOCK Tamper Registers Lock (Write-once, cleared by VDDCORE reset)
| Value | Name | Description |
|---|---|---|
| 0 | UNLOCKED | RTC_TMR and RTC_TDPR can be written. |
| 1 | LOCKED | RTC_TMR and RTC_TDPR cannot be written until the next VDDCORE domain reset. |
Bits 16, 17, 18, 19, 20, 21, 22, 23 – POLx WKUPx+1 Polarity
| Value | Name | Description |
|---|---|---|
| 0 | LOW | If the source of tamper remains low for a debounce period, a tamper event is generated. |
| 1 | HIGH | If the source of tamper remains high for a debounce period, a tamper event is generated. |
Bits 0, 1, 2, 3, 4, 5, 6, 7 – ENx WKUPx+1 Tamper Source Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | WKUP pin index x+1 is not enabled as a source of tamper. |
| 1 | ENABLE | WKUP pin index x+1 is enabled as a source of tamper. |