This register is cleared
after read and the read access also performs a clear on RTC_TSTRx and RTC_TSDRx.
The following configuration values are valid for all listed bit
names of this register:
0: No alarm generated since the
last clear.
1: An alarm has been generated by the
corresponding monitor since the last clear.
Name:
RTC_TSSRx
Offset:
0xB8 + x*0x0C [x=0..1]
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
DET7
DET6
DET5
DET4
DET3
DET2
DET1
DET0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
Access
Reset
Bits 16, 17, 18, 19, 20, 21, 22, 23 – DETx Tamper
Detection on VDDCORE WKUP[8:1] (cleared on read)
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