This configuration is relevant only if UTC = 1 in RTC_MR.
This register can only be written if the WPEN bit is cleared in the System
Controller Write Protection Mode register (SYSC_WPMR).
Name:
RTC_TIMR (UTC_MODE)
Offset:
0x08
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
UTC_TIME[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
UTC_TIME[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
UTC_TIME[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
UTC_TIME[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – UTC_TIME[31:0] Current UTC Time
Any value can be set.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.