18.6.24 RTC Tamper Debounce Period Register
| Name: | RTC_TDPR |
| Offset: | 0x5C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SELP7 | SELP6 | SELP5 | SELP4 | SELP3 | SELP2 | SELP1 | SELP0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PERB[3:0] | PERA[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 16, 17, 18, 19, 20, 21, 22, 23 – SELPx WKUPx+1 Debounce Period Selection
| Value | Name | Description |
|---|---|---|
| 0 | SEL_PA | WKUP pin index x+1 is debounced with PERA period. |
| 1 | SEL_PB | WKUP pin index x+1 is debounced with PERB period. |
Bits 7:4 – PERB[3:0] Debounce Period B
| Value | Name | Description |
|---|---|---|
| 0 | MD_SLCK_2 | The source of tamper must remain active for at least 2 monitoring domain slow clock cycles to generate a tamper event. |
| 1 | MD_SLCK_4 | The source of tamper must remain active for at least 4 monitoring domain slow clock cycles to generate a tamper event. |
| 2 | MD_SLCK_8 | The source of tamper must remain active for at least 8 monitoring domain slow clock cycles to generate a tamper event. |
| 3 | MD_SLCK_16 | The source of tamper must remain active for at least 16 monitoring domain slow clock cycles to generate a tamper event. |
| 4 | MD_SLCK_32 | The source of tamper must remain active for at least 32 monitoring domain slow clock cycles to generate a tamper event. |
| 5 | MD_SLCK_64 | The source of tamper must remain active for at least 64 monitoring domain slow clock cycles to generate a tamper event. |
| 6 | MD_SLCK_128 | The source of tamper must remain active for at least 128 monitoring domain slow clock cycles to generate a tamper event. |
| 7 | MD_SLCK_256 | The source of tamper must remain active for at least 256 monitoring domain slow clock cycles to generate a tamper event. |
Bits 3:0 – PERA[3:0] Debounce Period A
| Value | Name | Description |
|---|---|---|
| 0 | MD_SLCK_2 | The source of tamper must remain active for at least 2 monitoring domain slow clock cycles to generate a tamper event. |
| 1 | MD_SLCK_4 | The source of tamper must remain active for at least 4 monitoring domain slow clock cycles to generate a tamper event. |
| 2 | MD_SLCK_8 | The source of tamper must remain active for at least 8 monitoring domain slow clock cycles to generate a tamper event. |
| 3 | MD_SLCK_16 | The source of tamper must remain active for at least 16 monitoring domain slow clock cycles to generate a tamper event. |
| 4 | MD_SLCK_32 | The source of tamper must remain active for at least 32 monitoring domain slow clock cycles to generate a tamper event. |
| 5 | MD_SLCK_64 | The source of tamper must remain active for at least 64 monitoring domain slow clock cycles to generate a tamper event. |
| 6 | MD_SLCK_128 | The source of tamper must remain active for at least 128 monitoring domain slow clock cycles to generate a tamper event. |
| 7 | MD_SLCK_256 | The source of tamper must remain active for at least 256 monitoring domain slow clock cycles to generate a tamper event. |