18.6.10 RTC Status Register
Name: | RTC_SR |
Offset: | 0x18 |
Reset: | 0x00000004 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TDERR | CALEV | TIMEV | SEC | ALARM | ACKUPD | ||||
Access | R | R | R | R | R | R | |||
Reset | 0 | 0 | 0 | 1 | 0 | 0 |
Bit 5 – TDERR Time and/or Date Free Running Error
If the RTC is configured in UTC mode, the value returned by this field is not relevant.
Value | Name | Description |
---|---|---|
0 | CORRECT |
The internal free running counters are carrying valid values since the last read of the Status register (RTC_SR). |
1 | ERR_TIMEDATE |
The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. |
Bit 4 – CALEV Calendar Event
Value | Name | Description |
---|---|---|
0 | NO_CALEVENT | No calendar event has occurred since the last clear. |
1 | CALEVENT | At least one calendar event has occurred since the last clear. |
Bit 3 – TIMEV Time Event
Value | Name | Description |
---|---|---|
0 | NO_TIMEVENT | No time event has occurred since the last clear. |
1 | TIMEVENT | At least one time event has occurred since the last clear. |
Bit 2 – SEC Second Event
Value | Name | Description |
---|---|---|
0 | NO_SECEVENT | No second event has occurred since the last clear. |
1 | SECEVENT | At least one second event has occurred since the last clear. |
Bit 1 – ALARM Alarm Flag
Value | Name | Description |
---|---|---|
0 | NO_ALARMEVENT | No alarm matching condition occurred. |
1 | ALARMEVENT | An alarm matching condition has occurred. |
Bit 0 – ACKUPD Acknowledge for Update
Value | Name | Description |
---|---|---|
0 | FREERUN | Time and calendar registers cannot be updated. |
1 | UPDATE | Time and calendar registers can be updated. |