58.6.5.1 Read Timings

Table 58-28. SMC Read Signals - NRD-controlled (READ_MODE = 1)(1)
Symbol Parameter Conditions Min Max Unit
NO HOLD SETTINGS (NRD_HOLD = 0)
SMC1 Data setup before NRD high 3.3V domain 16 – ns
1.8V domain 18 – ns
SMC2 Data hold after NRD high 3.3V domain 0 – ns
1.8V domain 0 – ns
HOLD SETTINGS (NRD_HOLD ≠ 0)
SMC3 Data setup before NRD high 3.3V domain 12.8 – ns
1.8V domain 15.1 – ns
SMC4 Data hold after NRD high 3.3V domain 0 – ns
1.8V domain 0 – ns
HOLD or NO HOLD SETTINGS (NRD_HOLD ≠ 0, NRD_HOLD = 0)
SMC5 A0–A22 valid before NRD high 3.3V domain (NRD_SETUP + NRD_PULSE)

× tCPMCK - 10

 – ns
1.8V domain (NRD_SETUP + NRD_PULSE)

× tCPMCK - 8.7

 – ns
SMC6 NCS low before NRD high 3.3V domain (NRD_SETUP + NRD_PULSE - NCS_RD_SETUP) × tCPMCK - 9.9 – ns
1.8V domain (NRD_SETUP + NRD_PULSE - NCS_RD_SETUP) × tCPMCK - 8.5 – ns
SMC7 NRD pulse width 3.3V domain NRD_PULSE × tCPMCK - 0.1 – ns
1.8V domain NRD_PULSE × tCPMCK - 0.2 – ns
Note:
  1. The data provided in this table are extracted from circuit simulation results.

Table 58-29. SMC Read Signals - NCS-controlled (READ_MODE= 0)(1)
Symbol Parameter Conditions Min Max Unit
NO HOLD SETTINGS (NCS_RD_HOLD = 0)
SMC8 Data setup before NCS high 3.3V domain 24.3 – ns
1.8V domain 24.9 – ns
SMC9 Data hold after NCS high 3.3V domain 0 – ns
1.8V domain 0 – ns
HOLD SETTINGS (NCS_RD_HOLD ≠ 0)
SMC10 Data setup before NCS high 3.3V domain 21.9 – ns
1.8V domain 22.6 – ns
SMC11 Data hold after NCS high 3.3V domain 0 – ns
1.8V domain 0 – ns
HOLD or NO HOLD SETTINGS (NCS_RD_HOLD ≠ 0, NCS_RD_HOLD = 0)
SMC12 A0–A22 Valid before NCS High 3.3V domain (NCS_RD_SETUP + NCS_RD_PULSE)

× tCPMCK - 8.6

 – ns
1.8V domain (NCS_RD_SETUP + NCS_RD_PULSE)

× tCPMCK - 7.2

 – ns
SMC13 NRD low before NCS High 3.3V domain (NCS_RD_SETUP + NCS_RD_PULSE -

NRD_SETUP) × tCPMCK - 0.4

 – ns
1.8V domain (NCS_RD_SETUP + NCS_RD_PULSE -

NRD_SETUP) × tCPMCK - 0.5

 – ns
SMC14 NCS pulse width 3.3V domain NCS_RD_PULSE × tCPMCK - 2.8 – ns
1.8V domain NCS_RD_PULSE × tCPMCK - 1.5 – ns
Note:
  1. The data provided in this table are extracted from circuit simulation results.