40.6.2 Network Configuration Register
| Name: | EMAC_NCFGR |
| Offset: | 0x04 |
| Reset: | 0x00000800 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| IRXFCS | EFRHD | DRFCS | RLCE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RBOF[1:0] | PAE | RTY | CLK[1:0] | BIG | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 1 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UNI | MTI | NBC | CAF | JFRAME | FD | SPD | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 19 – IRXFCS Ignore RX FCS
| Value | Description |
|---|---|
| 0 | Normal operation |
| 1 | Frames with FCS/CRC errors are not rejected and no FCS error statistics are counted. |
Bit 18 – EFRHD Enable Frames Received in Half Duplex
Enable Frames to be received in half-duplex mode while transmitting.
Bit 17 – DRFCS Discard Receive FCS
When set, the FCS field of received frames is not copied to memory.
Bit 16 – RLCE Receive Length Field Checking Enable
When set, frames with measured lengths shorter than their length fields are discarded. Frames containing a type ID in bytes 13 and 14 — length/type ID = 0600 — are not counted as length errors.
Bits 15:14 – RBOF[1:0] Receive Buffer Offset
Indicates the number of bytes by which the received data is offset from the start of the first receive buffer.
| Value | Name | Description |
|---|---|---|
| 0 | OFFSET_0 | No offset from start of receive buffer |
| 1 | OFFSET_1 | One-byte offset from start of receive buffer |
| 2 | OFFSET_2 | Two-byte offset from start of receive buffer |
| 3 | OFFSET_3 | Three-byte offset from start of receive buffer |
Bit 13 – PAE Pause Enable
When set, transmission pauses when a valid pause frame is received.
Bit 12 – RTY Retry Test
| Value | Description |
|---|---|
| 0 | Normal operation |
| 1 | The back off between collisions is always one slot time. Setting this bit helps in testing the ‘too many retries’ condition. Also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every rx_clk cycle. |
Bits 11:10 – CLK[1:0] MDC Clock Divider
Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations).
| Value | Name | Description |
|---|---|---|
| 0 | MCK_8 | MCK divided by 8 (MCK up to 20 MHz) |
| 1 | MCK_16 | MCK divided by 16 (MCK up to 40 MHz) |
| 2 | MCK_32 | MCK divided by 32 (MCK up to 80 MHz) |
| 3 | MCK_64 | MCK divided by 64 (MCK up to 160 MHz) |
Bit 8 – BIG Receive 1536 Bytes Frames
Setting this bit means the EMAC receives frames up to 1536 bytes in length. Normally, the EMAC would reject any frame above 1518 bytes.
Bit 7 – UNI Unicast Hash Enable
When set to one, unicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register.
Bit 6 – MTI Multicast Hash Enable
When set to one, multicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register.
Bit 5 – NBC No Broadcast
When set to one, frames addressed to the broadcast address of all ones are not received.
Bit 4 – CAF Copy All Frames
When set to one, all valid frames are received.
Bit 3 – JFRAME Jumbo Frames
Set to one to enable jumbo frames of up to 10240 bytes to be accepted.
Bit 1 – FD Full Duplex
If set to one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting.
Bit 0 – SPD Speed
| Value | Description |
|---|---|
| 0 | 10 Mbit/s operation |
| 1 | 100 Mbit/s operation |