21.5.1.5 Sleep Mode Operation

In Standby mode, the low-power voltage regulator (LPVREG) is used to supply VDDCORE.

When the Run in Standby bit in the VREG register (VREG.RUNSTDBY) is written to '1', VDDCORE is supplied by the main voltage regulator. Depending on the Standby in PL0 bit in the Voltage Regulator register (VREG.STDBYPL0), the VDDCORE level is either set to the PL0 voltage level, or remains in the current performance level.

Table 21-2. VDDCORE Level in Standby Mode
VREG.RUNSTDBYVREG.STDBYPL0VDDCORE Supply in Standby Mode
0-LPVREG
10MAINVREG in current performance level(1)
11MAINVREG in PL0
Note:
  1. When the device is in PL0 but VREG.STDBYPL0=0, the MAINVREG is operating in normal power mode. To minimize power consumption, operate MAINVREG in PL0 mode by selecting VREG.STDBYPL0=1.

By writing the Low-Power mode Efficiency bit in the VREG register (VREG.LPEFF) to '1', the efficiency of the regulator in LPVREG can be improved when the application uses a limited VDD/AVDD range (2.5 to 3.63V). It is also possible to use the BOD33 in order to monitor the VDD/AVDD and change this LPEFF value on the fly according to VDD/AVDD level.

The VREGPLL voltage regulator has a similar behavior as the main voltage regulator, with some differences:
  • VREGPLL continuously run in standby mode if the Run in Standby bit in the VREGPLL register is (VREGPLL.RUNSTDBY=1) set and the regulator is enabled (VREGPLL.ENABLE = 1). This mode allows faster start-up times when sleep walking tasks must be executed.
  • When VREGPLL is enabled (VREGPLL.ENABLE = 1) and Standby bit in the VREGPLL register is cleared (VREGPLL.RUNSTDBY=0), the VREGPLL is internally enabled when a sleep walking task must be executed, using the DFLLULP, DFLL or FDPLL clock sources. In this operating mode, the start-up time needed before executing a sleep walking task will be longer, as the voltage level must be stable before execution starts.
Table 21-3. VDDPLL Level in Standby Mode
VREGPLL.RUNSTDBYVREG.STDBYPL0VDDPLL Supply in Standby Mode
0-ON/OFF(1)
10VREGPLL in current performance level(2)
11VREGPLL in PL0
Note:
  1. Depending on sleep walking requests and VREGPLL.RUNSTDBY bit setting.
  2. When the device is in PL0 but VREG.STDBYPL0=0, the VREGPLL is operating in normal power mode. To minimize power consumption, operate VREGPLL in PL0 mode by selecting VREG.STDBYPL0=1.