21.5.1.1 Enabling, Disabling, and Resetting

The LDO main voltage regulator is enabled after any Reset. The main voltage regulator (MAINVREG) can not be disabled, hence the Enable bit in the VREG register (VREG.ENABLE) must be set to one. The main voltage regulator output supply level is automatically defined by the performance level or the Sleep mode selected in the Power Manager module.

The FDPLL96M/DFLL48M/DFLLULP voltage regulator (VREGPLL) is enabled by writing the Enable bit in VREGPLL register (VREGPLL.ENABLE) to one. As for the main regulator, the VREGPLL output supply level is automatically defined by the performance level or the sleep mode selected in the Power Manager module.

The VREGPLL is disabled by writing the Enable bit in VREGPLL register (VREGPLL.ENABLE) to zero. When the regulator is disabled, the power domain power domain is shut-off and pending FDPLL96M/DFLL48M/DFLLULP clock requests will not be serviced. As a consequence, it is recommended to shut-down the peripherals using these clock sources before disabling the VREGPLL.