21.5.1.3 Selecting MAINVREG and VREGPLL Voltage Regulators

In Active mode, the type of the main voltage regulator supplying VDDCORE can be switched on the fly. The two alternatives are a LDO regulator and a Buck converter.

The main voltage regulator switching sequences are as follows:

  • The user changes the value of the Voltage Regulator Selection bit in the Voltage Regulator System Control register (VREG.SEL)
  • The start of the switching sequence is indicated by clearing the Voltage Regulator Ready bit in the STATUS register (STATUS.VREGRDY=0)
  • Once the switching sequence is completed, STATUS.VREGRDY will read '1'
The Voltage Regulator Ready (VREGRDY) interrupt can also be used to detect a zero-to-one transition of the STATUS.VREGRDY bit.
If one of the FDPLL96M DFLL48M or DFLLULP clock sources must be used by the application, the user must enable the VREGPLL regulator. To configure in a safe way the system, the user must follow the sequence:
  • Wait until the main regulator is ready (STATUS.VREGRDY = 1)
  • Optionally enable the PLL Oscillators Core Voltage Regulator Ready Interrupt (INTENSET.VCOREPLLRDY)
  • Enable the PLL oscillators regulator (VREGPLL.ENABLE)
  • Wait for VCOREPLLRDY interrupt or poll the VCOREPLLRDY bit STATUS register (STATUS.VCOREPLLRDY)

The clock sources must be enabled only when the VDDPLL supply is established. When enabled, the VREGPLL regulator remains enabled in all sleep modes, except Standby sleep mode, where the regulator supports the Sleep Walking capability.