31.7.17 Interrupt Flag Status and Clear
Important: This register is only
available for PIC32CM LS00/LS60 and has no effect for
PIC32CM LE00.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins.
Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own
PORT registers, with a 0x80 address spacing. For example, the register address offset for
the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register
address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
| Name: | INTFLAG |
| Offset: | 0x68 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NSCHK | |||||||||
| Access | RW/RW/RW | ||||||||
| Reset | 0 |
Bit 0 – NSCHK Non-Secure Check
This flag is set on NONSEC write when a bit in NSCHK is 1 and the corresponding bit in NONSEC is cleared, or when a bit in NSCHK is 0 and the corresponding bit in NONSEC is set.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Secure Check interrupt flag.