31.7.16 Interrupt Enable Set
Important: This register is only available for PIC32CM LS00/LS60 and has no effect for PIC32CM LE00.
This register allows the user
to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).Tip: The I/O pins are assembled in pin groups
(”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB
pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For
example, the register address offset for the Data Direction (DIR) register for group 0 (PA00
to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to
PB31) is 0x80.
| Name: | INTENSET |
| Offset: | 0x64 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NSCHK | |||||||||
| Access | RW/RW/RW | ||||||||
| Reset | 0 |
Bit 0 – NSCHK Non-Secure Check Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Non-Secure Check Interrupt Enable bit, which enables the Non-Secure Check interrupt.
| Value | Description |
|---|---|
| 0 | The Non-Secure Check interrupt is disabled. |
| 1 | The Non-Secure Check interrupt is enabled. |