31.7.19 Security Attribution Check
Important: This register is only available for
PIC32CM LS00/LS60 and has no effect for
PIC32CM LE00.
This register
allows the user to select one or more pins to check their security attribution as
non-secured.Tip: The I/O pins are assembled in pin groups (”PORT groups”)
with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc.
Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the
register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31)
is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31)
is 0x80.
Name: | NSCHK |
Offset: | 0x70 |
Reset: | 0x00000000 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
NSCHK[31:24] | |||||||||
Access | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
NSCHK[23:16] | |||||||||
Access | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
NSCHK[15:8] | |||||||||
Access | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NSCHK[7:0] | |||||||||
Access | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | RW/RW/RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:0 – NSCHK[31:0] Port Security Attribution Check
These bits select the individual pins for security attribution check. If any pin selected in NSCHK has the corresponding bit in NONSEC set to the opposite value, then the NSCHK interrupt flag will be set.
Value | Description |
---|---|
0 | 0-to-1 transition will be detected on corresponding NONSEC bit. |
1 | 1-to-0 transition will be detected on corresponding NONSEC bit. |