31.7 Register Summary

Refer to the Registers Description section for more details on register properties and access permissions.

Important: (PIC32CM LS00 only)

The peripheral register map is automatically duplicated in a Secure and Non-Secure alias:

  • The Non-Secure alias is at the peripheral base address
  • The Secure alias is located at the peripheral base address + 0x200

Refer to Mix-Secure Peripherals for more information on register access rights.

OffsetNameBit Pos.76543210
0x00DIR31:24DIR[31:24]
23:16DIR[23:16]
15:8DIR[15:8]
7:0DIR[7:0]
0x04DIRCLR31:24DIRCLR[31:24]
23:16DIRCLR[23:16]
15:8DIRCLR[15:8]
7:0DIRCLR[7:0]
0x08DIRSET31:24DIRSET[31:24]
23:16DIRSET[23:16]
15:8DIRSET[15:8]
7:0DIRSET[7:0]
0x0CDIRTGL31:24DIRTGL[31:24]
23:16DIRTGL[23:16]
15:8DIRTGL[15:8]
7:0DIRTGL[7:0]
0x10OUT31:24OUT[31:24]
23:16OUT[23:16]
15:8OUT[15:8]
7:0OUT[7:0]
0x14OUTCLR31:24OUTCLR[31:24]
23:16OUTCLR[23:16]
15:8OUTCLR[15:8]
7:0OUTCLR[7:0]
0x18OUTSET31:24OUTSET[31:24]
23:16OUTSET[23:16]
15:8OUTSET[15:8]
7:0OUTSET[7:0]
0x1COUTTGL31:24OUTTGL[31:24]
23:16OUTTGL[23:16]
15:8OUTTGL[15:8]
7:0OUTTGL[7:0]
0x20IN31:24IN[31:24]
23:16IN[23:16]
15:8IN[15:8]
7:0IN[7:0]
0x24CTRL31:24SAMPLING[31:24]
23:16SAMPLING[23:16]
15:8SAMPLING[15:8]
7:0SAMPLING[7:0]
0x28WRCONFIG31:24HWSELWRPINCFG WRPMUXPMUX[3:0]
23:16 DRVSTR   PULLENINENPMUXEN
15:8PINMASK[15:8]
7:0PINMASK[7:0]
0x2CEVCTRL31:24PORTEI3EVACT3[1:0]PID3[4:0]
23:16PORTEI2EVACT2[1:0]PID2[4:0]
15:8PORTEI1EVACT1[1:0]PID1[4:0]
7:0PORTEI0EVACT0[1:0]PID0[4:0]
0x30PMUX07:0PMUXO[3:0]PMUXE[3:0]
...        
0x3FPMUX157:0PMUXO[3:0]PMUXE[3:0]
0x40PINCFG07:0 DRVSTR   PULLENINENPMUXEN
...        
0x5FPINCFG317:0 DRVSTR   PULLENINENPMUXEN
0x60INTENCLR31:24        
23:16        
15:8        
7:0       NSCHK
0x64INTENSET31:24        
23:16        
15:8        
7:0       NSCHK
0x68INTFLAG31:24        
23:16        
15:8        
7:0       NSCHK
0x6CNONSEC31:24NONSEC[31:24]
23:16NONSEC[23:16]
15:8NONSEC[15:8]
7:0NONSEC[7:0]
0x70NSCHK31:24NSCHK[31:24]
23:16NSCHK[23:16]
15:8NSCHK[15:8]
7:0NSCHK[7:0]