15.6.14 Peripheral Non-Secure Status - Bridge C
Important: This register is only
available for PIC32CM LS00/LS60 and has no effect
for PIC32CM LE00.
This register is loaded from UROW at boot.
Reading NONSECC register returns peripheral Security Attribution status:
| Value | Description |
|---|---|
| 0 | Peripheral is secured. |
| 1 | Peripheral is non-secured. |
| Name: | NONSECC |
| Offset: | 0x5C |
| Reset: | x initially determined from NVM User Row after reset |
| Property: | Write-Secure |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRAM | OPAMP | I2S | CCL | TRNG | PTC | ||||
| Access | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | |||
| Reset | x | x | x | x | x | x |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DAC | ADC | TCC3 | TCC2 | TCC1 | TCC0 | TC2 | TC1 | ||
| Access | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | |
| Reset | x | x | x | x | x | x | x | x |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TC0 | SERCOM5 | SERCOM4 | SERCOM3 | SERCOM2 | SERCOM1 | SERCOM0 | EVSYS | ||
| Access | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | |
| Reset | x | x | x | x | x | x | x | x |