15.6.12 Peripheral Non-Secure Status - Bridge A
Important: This register is only
available for PIC32CM LS00/LS60 and has no effect
for PIC32CM LE00.
This register is loaded from UROW at boot.
Reading NONSECA register returns peripheral security attribution status:
| Value | Description |
|---|---|
| 0 | Peripheral is secured. |
| 1 | Peripheral is non-secured. |
| Name: | NONSECA |
| Offset: | 0x54 |
| Reset: | x initially determined from NVM User Row after reset |
| Property: | Write-Secure |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Reserved | Reserved | AC | PORT | FREQM | EIC | RTC | WDT | ||
| Access | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | |
| Reset | x | x | x | x | x | x | x | x |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GCLK | SUPC | OSC32KCTRL | OSCCTRL | RSTC | MCLK | PM | PAC | ||
| Access | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | |
| Reset | x | x | x | x | x | x | x | x |
Bit 15 – Reserved
Bit 14 – Reserved
Bit 13 – AC Peripheral AC Non-Secure
Bit 12 – PORT Peripheral PORT Non-Secure
Bit 11 – FREQM Peripheral FREQM Non-Secure
Bit 10 – EIC Peripheral EIC Non-Secure
Bit 9 – RTC Peripheral RTC Non-Secure
Bit 8 – WDT Peripheral WDT Non-Secure
Bit 7 – GCLK Peripheral GCLK Non-Secure
Bit 6 – SUPC Peripheral SUPC Non-Secure
Bit 5 – OSC32KCTRL Peripheral OSC32KCTRL Non-Secure
Bit 4 – OSCCTRL Peripheral OSCCTRL Non-Secure
Bit 3 – RSTC Peripheral RSTC Non-Secure
Bit 2 – MCLK Peripheral MCLK Non-Secure
Bit 1 – PM Peripheral PM Non-Secure
Bit 0 – PAC Peripheral PAC Non-Secure
The PAC Peripheral is always secured if BOCOR.SECCFGLOCK == 1 after exiting the Boot ROM (NONSECA.PAC=0).