10.1.7.7 Synchronous Serial Controller (SSC)
Timings are provided in the following conditions:
- 1.8V domain: VDDIO from 1.7V to 1.9V, maximum external capacitor = 10 pF, DRV = 1, SR = 1
- 3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 10 pF, DRV = 0, SR = 1
| Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|
| SSC TX Timings - Client Mode (TK Input) | |||||
| fTK | TK frequency (TK input) | – | – | 25.0 | MHz |
| tTK | Minimum TK period | – | 40.0 | – | ns |
| SSC1 | TK edge to TF/TD | – | 4.0 | 15.0 | ns |
| SSC5 | TF setup time before TK edge | – | 0.0 | – | ns |
| SSC6 | TF hold time after TK edge | – | tMCK | – | ns |
| SSC7 | TK edge to TF/TD with STDDLY = 0, START = 4,5,7 | 3 x tMCK + | 4.0 | 15.0 | ns |
| SSC TX Timings - Host Mode (TK Output) | |||||
| fTK | TK frequency (TK output) | – | – | 26.7 | MHz |
| tTK | Minimum TK period | – | 37.5 | – | ns |
| SSC0 | TK edge to TF/TD | – | -3.8 | 9.4 | ns |
| SSC2 | TF setup time before TK edge | – | 13.1 | – | ns |
| SSC3 | TF hold time after TK edge | – | 5.3 | – | ns |
| SSC4 | TK edge to TF/TD with STDDLY = 0, START = 4,5,7 | 2 x tMCK + | -3.8 | 9.4 | ns |
| SSC14 | TK rise time or fall time (TK input) | – | – | 10.0 | ns |
| SSC RX Timings - Client Mode (RK Input) | |||||
| fRK | RK frequency (RK input) | – | – | 25.0 | MHz |
| tRK | Minimum RK period | – | 40.0 | – | ns |
| SSC8 | RF/RD setup time before RK edge | – | 0.0 | – | ns |
| SSC9 | RF/RD hold time after RK edge | – | tMCK | – | ns |
| SSC10 | RK edge to RF | – | 4.0 | 15.0 | ns |
| SSC RX Timings - Host Mode (RK Output) | |||||
| fRK | RK frequency (RK output) | – | – | 26.7 | MHz |
| tRK | Minimum RK period | – | 37.5 | – | ns |
| SSC11 | RD/RF setup time before RK edge | – | 13.1 | – | ns |
| SSC12 | RD/RF hold time after RK edge (RF input) | – | 5.3 | – | ns |
| SSC13 | RK edge to RF | – | -3.8 | 9.4 | ns |
