7.6.6.18 PUF Hardware Restrict User Context 1 Register

Values in this register are static and not managed by the PUF.
Name: PUF_HW_RUC1
Offset: 0x0E4
Reset: 
Property: Read-only

Bit 3130292827262524 
 RUC31RUC30RUC29RUC28RUC27RUC26RUC25RUC24 
Access RRRRRRRR 
Reset  
Bit 2322212019181716 
 RUC23RUC22RUC21RUC20RUC19RUC18RUC17RUC16 
Access RRRRRRRR 
Reset  
Bit 15141312111098 
 RUC15RUC14RUC13RUC12RUC11RUC10RUC9RUC8 
Access RRRRRRRR 
Reset  
Bit 76543210 
 RUC7RUC6RUC5RUC4RUC3RUC2RUC1RUC0 
Access RRRRRRRR 
Reset  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – RUCx Restrict User Context Bit x

These bits are controlled by the SFR during the boot sequence and cannot be modified after the boot period.
ValueDescription
0 This bit can be used in the user context 1 field.
1 This bit cannot be used in the user context 1 field.