The following configuration values are valid for all listed bit names of this register:
0: Disables the corresponding interrupt source.
1: Enables the corresponding interrupt source.
Name:
PUF_IMR
Offset:
0x014
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
RESEEDR
RESEEDW
Access
R/W
R/W
Reset
0
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
DOREQ
DIREQ
REJECTED
ZEROIZED
ERROR
OK
BUSY
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit 30 – RESEEDR Reseed Action Required Event
Bit 29 – RESEEDW Reseed Warning Event
Bit 6 – DOREQ Data Out Request Event
Bit 5 – DIREQ Data In Request Event
Bit 4 – REJECTED Last Activation Code Rejection Event
Bit 3 – ZEROIZED Zeroized Operation Completed Event
Bit 2 – ERROR Last Operation Fail Event
Bit 1 – OK Last Operation Successful Achievement Event
Bit 0 – BUSY Operation Start Event
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