The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding operation.
Note: Only one command bit must be activated at a time, except ZEROIZE. Writing
ZEROIZE=1 takes precedence over all other commands.
Name:
PUF_CR
Offset:
0x000
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
TESTPUF
TESTMEM
Access
R/W
R/W
Reset
0
0
Bit
23
22
21
20
19
18
17
16
RESEED
Access
R/W
Reset
0
Bit
15
14
13
12
11
10
9
8
GENRAND
WRAP
WGENRAND
Access
R/W
R/W
R/W
Reset
0
0
0
Bit
7
6
5
4
3
2
1
0
UNWRAP
GETKEY
STOP
RECO
START
ENROLL
ZEROIZE
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit 31 – TESTPUF Test PUF Operation
Bit 30 – TESTMEM Test Memory Operation
Bit 16 – RESEED Reseed Operation
Bit 15 – GENRAND Generate Random Operation
Bit 9 – WRAP Wrap Operation
Bit 8 – WGENRAND Wrap Generated Random Operation
Bit 7 – UNWRAP Unwrap Operation
Bit 6 – GETKEY Get Key Operation
Bit 5 – STOP Stop Operation
Bit 3 – RECO Reconstruct Operation
Bit 2 – START Start Operation
Bit 1 – ENROLL Enroll Operation
Bit 0 – ZEROIZE Zeroize Operation
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
