Introduction
Reference Document
1 Overview
2 CPU and Interconnect
3 Memories
4 System Controller
5 Image Subsystem
6 Audio Subsystem
7 Security and Cryptography Subsystem
8 Connectivity Subsystem
- 8.1 Overview
- 8.2 Ethernet MAC (GMAC)
- 8.3 Flexible Serial Communication Controller (FLEXCOM)
  - 8.3.1 Description
  - 8.3.2 Embedded Characteristics
  - 8.3.3 Block Diagram
  - 8.3.4 I/O Lines Description
  - 8.3.5 Product Dependencies
  - 8.3.6 Register Accesses
  - 8.3.7 USART Functional Description
  - 8.3.8 SPI Functional Description
  - 8.3.9 TWI Functional Description
  - 8.3.10 Register Summary
    - 8.3.10.1 FLEXCOM Mode Register
      FLEXCOM Mode Register
    - 8.3.10.2 FLEXCOM Receive Holding Register
      FLEXCOM Receive Holding Register
    - 8.3.10.3 FLEXCOM Transmit Holding Register
      FLEXCOM Transmit Holding Register
    - 8.3.10.4 USART Control Register
      USART Control Register
    - 8.3.10.5 USART Mode Register
      USART Mode Register
    - 8.3.10.6 USART Interrupt Enable Register (Default Mode)
      USART Interrupt Enable Register (Default Mode)
    - 8.3.10.7 USART Interrupt Enable Register (LIN_MODE)
      USART Interrupt Enable Register (LIN_MODE)
    - 8.3.10.8 USART Interrupt Enable Register (LON_MODE)
      USART Interrupt Enable Register (LON_MODE)
    - 8.3.10.9 USART Interrupt Disable Register (Default Mode)
      USART Interrupt Disable Register (Default Mode)
    - 8.3.10.10 USART Interrupt Disable Register (LIN_MODE)
      USART Interrupt Disable Register (LIN_MODE)
    - 8.3.10.11 USART Interrupt Disable Register (LON_MODE)
      USART Interrupt Disable Register (LON_MODE)
    - 8.3.10.12 USART Interrupt Mask Register (Default Mode)
      USART Interrupt Mask Register (Default Mode)
    - 8.3.10.13 USART Interrupt Mask Register (LIN_MODE)
      USART Interrupt Mask Register (LIN_MODE)
    - 8.3.10.14 USART Interrupt Mask Register (LON_MODE)
      USART Interrupt Mask Register (LON_MODE)
    - 8.3.10.15 USART Channel Status Register (Default Mode)
      USART Channel Status Register (Default Mode)
    - 8.3.10.16 USART Channel Status Register (LIN_MODE)
      USART Channel Status Register (LIN_MODE)
    - 8.3.10.17 USART Channel Status Register (LON_MODE)
      USART Channel Status Register (LON_MODE)
    - 8.3.10.18 USART Receive Holding Register (Default Mode)
      USART Receive Holding Register (Default Mode)
    - 8.3.10.19 USART Receive Holding Register (FIFO Multi Data)
      USART Receive Holding Register (FIFO Multi Data)
    - 8.3.10.20 USART Transmit Holding Register (Default Mode)
      USART Transmit Holding Register (Default Mode)
    - 8.3.10.21 USART Transmit Holding Register (FIFO Multi Data)
      USART Transmit Holding Register (FIFO Multi Data)
    - 8.3.10.22 USART Baud Rate Generator Register
      USART Baud Rate Generator Register
    - 8.3.10.23 USART Receiver Timeout Register
      USART Receiver Timeout Register
    - 8.3.10.24 USART Transmitter Timeguard Register
      USART Transmitter Timeguard Register
    - 8.3.10.25 USART Transmitter Timeguard Register (LON_MODE)
      USART Transmitter Timeguard Register (LON_MODE)
    - 8.3.10.26 USART FI DI RATIO Register
      USART FI DI RATIO Register
    - 8.3.10.27 USART FI DI RATIO Register (LON_MODE)
      USART FI DI RATIO Register (LON_MODE)
    - 8.3.10.28 USART Number of Errors Register
      USART Number of Errors Register
    - 8.3.10.29 USART IrDA FILTER Register
      USART IrDA FILTER Register
    - 8.3.10.30 USART Manchester Configuration Register
      USART Manchester Configuration Register
    - 8.3.10.31 USART LIN Mode Register
      USART LIN Mode Register
    - 8.3.10.32 USART LIN Identifier Register
      USART LIN Identifier Register
    - 8.3.10.33 USART LIN Baud Rate Register
      USART LIN Baud Rate Register
    - 8.3.10.34 USART LON Mode Register
      USART LON Mode Register
    - 8.3.10.35 USART LON Preamble Register
      USART LON Preamble Register
    - 8.3.10.36 USART LON Data Length Register
      USART LON Data Length Register
    - 8.3.10.37 USART LON L2HDR Register
      USART LON L2HDR Register
    - 8.3.10.38 USART LON Backlog Register
      USART LON Backlog Register
    - 8.3.10.39 USART LON Beta1 Tx Register
      USART LON Beta1 Tx Register
    - 8.3.10.40 USART LON Beta1 Rx Register
      USART LON Beta1 Rx Register
    - 8.3.10.41 USART LON Priority Register
      USART LON Priority Register
    - 8.3.10.42 USART LON IDT Tx Register
      USART LON IDT Tx Register
    - 8.3.10.43 USART LON IDT Rx Register
      USART LON IDT Rx Register
    - 8.3.10.44 USART IC DIFF Register
      USART IC DIFF Register
    - 8.3.10.45 USART Comparison Register
      USART Comparison Register
    - 8.3.10.46 USART FIFO Mode Register
      USART FIFO Mode Register
    - 8.3.10.47 USART FIFO Level Register
      USART FIFO Level Register
    - 8.3.10.48 USART FIFO Interrupt Enable Register
      USART FIFO Interrupt Enable Register
    - 8.3.10.49 USART FIFO Interrupt Disable Register
      USART FIFO Interrupt Disable Register
    - 8.3.10.50 USART FIFO Interrupt Mask Register
      USART FIFO Interrupt Mask Register
    - 8.3.10.51 USART FIFO Event Status Register
      USART FIFO Event Status Register
    - 8.3.10.52 USART Write Protection Mode Register
      USART Write Protection Mode Register
    - 8.3.10.53 USART Write Protection Status Register
      USART Write Protection Status Register
    - 8.3.10.54 SPI Control Register
      SPI Control Register
    - 8.3.10.55 SPI Mode Register
      SPI Mode Register
    - 8.3.10.56 SPI Receive Data Register (Default Mode)
      SPI Receive Data Register (Default Mode)
    - 8.3.10.57 SPI Receive Data Register (FIFO Multiple Data, 8-bit)
      SPI Receive Data Register (FIFO Multiple Data, 8-bit)
    - 8.3.10.58 SPI Receive Data Register (FIFO Multiple Data, 16-bit)
      SPI Receive Data Register (FIFO Multiple Data, 16-bit)
    - 8.3.10.59 SPI Transmit Data Register (Default Mode)
      SPI Transmit Data Register (Default Mode)
    - 8.3.10.60 SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit)
      SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit)
    - 8.3.10.61 SPI Status Register
      SPI Status Register
    - 8.3.10.62 SPI Interrupt Enable Register
      SPI Interrupt Enable Register
    - 8.3.10.63 SPI Interrupt Disable Register
      SPI Interrupt Disable Register
    - 8.3.10.64 SPI Interrupt Mask Register
      SPI Interrupt Mask Register
    - 8.3.10.65 SPI Chip Select Register
      SPI Chip Select Register
    - 8.3.10.66 SPI FIFO Mode Register
      SPI FIFO Mode Register
    - 8.3.10.67 SPI FIFO Level Register
      SPI FIFO Level Register
    - 8.3.10.68 SPI Comparison Register
      SPI Comparison Register
    - 8.3.10.69 SPI CRC Register
      SPI CRC Register
    - 8.3.10.70 SPI Two-Pin Mode Register
      SPI Two-Pin Mode Register
    - 8.3.10.71 SPI Two-Pin Header Register
      SPI Two-Pin Header Register
    - 8.3.10.72 SPI Write Protection Mode Register
      SPI Write Protection Mode Register
    - 8.3.10.73 SPI Write Protection Status Register
      SPI Write Protection Status Register
    - 8.3.10.74 TWI Control Register (Default Mode)
      TWI Control Register (Default Mode)
    - 8.3.10.75 TWI Control Register (FIFO_ENABLED)
      TWI Control Register (FIFO_ENABLED)
    - 8.3.10.76 TWI Host Mode Register
      TWI Host Mode Register
    - 8.3.10.77 TWI Client Mode Register
      TWI Client Mode Register
    - 8.3.10.78 TWI Internal Address Register
      TWI Internal Address Register
    - 8.3.10.79 TWI Clock Waveform Generator Register
      TWI Clock Waveform Generator Register
    - 8.3.10.80 TWI Status Register (Default Mode)
      TWI Status Register (Default Mode)
    - 8.3.10.81 TWI Status Register (FIFO ENABLED)
      TWI Status Register (FIFO ENABLED)
    - 8.3.10.82 TWI Interrupt Enable Register
      TWI Interrupt Enable Register
    - 8.3.10.83 TWI Interrupt Disable Register
      TWI Interrupt Disable Register
    - 8.3.10.84 TWI Interrupt Mask Register
      TWI Interrupt Mask Register
    - 8.3.10.85 TWI Receive Holding Register (Default Mode)
      TWI Receive Holding Register (Default Mode)
    - 8.3.10.86 TWI Receive Holding Register (FIFO Enabled)
      TWI Receive Holding Register (FIFO Enabled)
    - 8.3.10.87 TWI Transmit Holding Register (Default Mode)
      TWI Transmit Holding Register (Default Mode)
    - 8.3.10.88 TWI Transmit Holding Register (FIFO Enabled)
      TWI Transmit Holding Register (FIFO Enabled)
    - 8.3.10.89 TWI SMBus Timing Register
      TWI SMBus Timing Register
    - 8.3.10.90 TWI High-Speed Register
      TWI High-Speed Register
    - 8.3.10.91 TWI Alternative Command Register
      TWI Alternative Command Register
    - 8.3.10.92 TWI Filter Register
      TWI Filter Register
    - 8.3.10.93 TWI High-Speed Clock Waveform Generator Register
      TWI High-Speed Clock Waveform Generator Register
    - 8.3.10.94 TWI FIFO Mode Register
      TWI FIFO Mode Register
    - 8.3.10.95 TWI FIFO Level Register
      TWI FIFO Level Register
    - 8.3.10.96 TWI FIFO Status Register
      TWI FIFO Status Register
    - 8.3.10.97 TWI FIFO Interrupt Enable Register
      TWI FIFO Interrupt Enable Register
    - 8.3.10.98 TWI FIFO Interrupt Disable Register
      TWI FIFO Interrupt Disable Register
    - 8.3.10.99 TWI FIFO Interrupt Mask Register
      TWI FIFO Interrupt Mask Register
    - 8.3.10.100 TWI Write Protection Mode Register
      TWI Write Protection Mode Register
    - 8.3.10.101 TWI Write Protection Status Register
      TWI Write Protection Status Register
- 8.4 Quad Serial Peripheral Interface (QSPI)
- 8.5 Secure Digital MultiMedia Card Controller (SDMMC)
- 8.6 Controller Area Network (MCAN)
- 8.7 Timer Counter (TC)
- 8.8 Pulse Width Modulation Controller (PWM)
9 USB Subsystem
10 Electrical and Mechanical Characteristics
11 Revision History
Microchip Information

8.3.10.70 SPI Two-Pin Mode Register

This register can only be written if WPEN is cleared in the SPI Write Protection Mode Register.

Name:	FLEX_SPI_TPMR
Offset:	0x450
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
					OSR[1:0]		ALWAYS0	CSM
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:2 – OSR[1:0] Oversampling Rate

Defines the MCP3910 OSR setting used.

Bit 1 – ALWAYS0 Always Written to 0

Bit 0 – CSM Chip Select Mode

Value	Description
0	Chip select is not driven.
1	Chip select is driven and can be used to control enable pin of the external device. Depending on FLEX_SPI_MR.PCSDEC, an external decoder can be used to minimize the number of IOs used.

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