5.3.7.3 LVDSC User Control Bits Register
This register can only be written if WPEN is cleared in LVDSC_WPMR.
| Name: | LVDSC_UCBR |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RESA3 | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 2 – RESA3 Lane A3 Reserved Bit Value
| Value | Description |
|---|---|
| 0 | Asserts a logical 0 on lane A3 reserved bit location. |
| 1 | Asserts a logical 1 on lane A3 reserved bit location. |