5.3.7.2 LVDSC Configuration Register
This register can only be written if WPEN is cleared in LVDSC_WPMR.
LVDSC_CR.SER_EN must be cleared to write in LVDSC_CFGR.
| Name: | LVDSC_CFGR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MAPPING | DC_BAL | LCDC_PIXSIZE | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 6 – MAPPING LVDS Mapping Format (Unbalanced mode only)
| Value | Name | Description |
|---|---|---|
| 0 | VESA | Maps LVDS lanes on VESA format. |
| 1 | JEIDA | Maps LVDS lanes on JEIDA format. |
Bit 5 – DC_BAL DC Mode
| Value | Name | Description |
|---|---|---|
| 0 | UNBALANCED | LVDS lane is DC-unbalanced. |
| 1 | BALANCED | LVDS lane is DC-balanced. |
Bit 0 – LCDC_PIXSIZE LCD Controller Pixel Size
| Value | Name | Description |
|---|---|---|
| 0 | 24BITS | LCD controller provides 24 bits per pixel. |
| 1 | 18BITS | LCD controller provides 18 bits per pixel. |