42.6.1.3 LCD Display

The display memory stores the values of all segments to display. The display memory is accessible through APB, and should be filled before the next frame starts. A start of a new frame triggers copying the display memory into the shadow display memory. A display memory refresh is thus possible without affecting data already sent to the panel.

Note: The display memory is not initialized at startup.

When a bit in the display memory is written to '1', the corresponding segment will be energized (ON / opaque), and de-energized (OFF / transparent) when this bit is written to '0'.

Each COM signal has identical waveforms but different phases. The maximum amplitude (VLCD) occurs during the corresponding phase of the frame (phase 0 for COM0, phase 1 for COM1 etc.). Otherwise, the signal amplitude is one of the bias voltages (depending on the bias setting).

The SEG lines are controlled according to the corresponding value in shadow display memory. For each phase of the frame, SEG lines are driven to VLCD and GND when the pixel is ON, or to one of the bias voltages when the pixel is OFF.