42.6.1.10 Saving Power with LowR and Buffer

The bias generation block generates the bias voltage that the LCD waveform needs. For intermediate bias levels between ground and VLCD, they are generated by an on-chip resistive voltage divider.

The voltage divider is made of two strings, one high resistance string and one low resistance string. The high resistance string is always on when the LCD is enabled. The low resistance string can be turned on for a configurable amount of time (defined in the SLCD controller) to increase the drive capability of the bias, at the price of increased power consumption. The on-time is aligned at waveform transition so that the best trade off can be found between power and waveform quality by tuning the ratio of the LowR on-time versus the waveform period to find the best trade-off. The LowR on-time is selected by writing the Low Resistance Enable Duration bits in the Control B register (CTRLB.LRD).

A buffer is also provided for each of the intermediate bias levels. The buffers have a fixed current consumption, but provide dynamic current drive capability. Similar to the LowR driver, the buffer can be turned on for only a portion of the waveform period after transition. This is tuned by writing to the Bias Buffer Enable bits in the Control B register (CTRLB.BBD).

Compared to LowR, buffers offer a higher drive capability with relatively fixed operating current, which achieve a better performance (waveform quality versus power consumption) when the panel represents a big capacitive load (i.e. 10nF).