42.6.1.8 LCD Power Supply
The LCD voltage levels are generated either from the VLCD pin or by the internal power supply block, through an internal resistor divider network. The internal power supply is selected by writing a '0' to the External VLCD bit in the Control A register (CTRLA.XVLCD); the external power supply is selected by writing a '1' to CTRLA.XVLCD.
The LCD power supply block generates up to three intermediate voltage levels (in internal or external supply mode), depending on the bias configuration bits in the CTRLA register (CTRLA.BIAS[1:0]).
| CTRLA.BIAS[1:0] | Configuration | Voltages |
|---|---|---|
| 00 | Static | VLCD |
| 01 | 1/2 | VLCD, 1/2 VLCD |
| 10 | 1/3 | VLCD, 2/3 VLCD, 1/3 VLCD |
| 11 | 1/4 | VLCD, 3/4 VLCD, 1/2 VLCD, 1/4 VLCD |
The VLCD Status bit in the STATUS register (STATUS.VLCDS) indicates the current relation of VLCD and VDD. When VDD33 > Target VLCD, STATUS.VLCDS is set to '1'. Otherwise, STATUS.VLCDS is cleared to '0'.
The voltage status of VLCD itself is indicated by STATUS.VLCDR: when the VLCD voltage is not well regulated to the target voltage, indicated by STATUS.VLCDR=0, the display quality may be impaired during the ongoing settling period. If the display quality is critical for the application, transient phenomena can be avoided by first disabling the COM/SEG output by writing CTRLD.DISPEN=0, then enable COM/SEG output again once the STATUS.VLCDR bit is set.