42.6.1.7 Display Memory Mapping

The display memory size depends on the configured duty ratio. For duty ratios above 1/4, the display memory is 44 bits wide per COM line. For 1/6 duty, the display memory is 42 bits wide per COM line, and for 1/8 duty, the display memory is 40 bits wide per COM line.

Figure 42-17. Display Memory Mapping

Direct Access

CPU can access display memory in direct access by writing to the corresponding Segments Data Low/High for COMx Line register (SDATAL/Hx). For each bit y of the SDATAL/Hx register there is a corresponding segment connected to SEG y line and COMx line. For example, to update the segment connected to SEG4/COM2, write to bit 4 of the SDATAL2 register.

Indirect Access

The CPU can also update the display memory in indirect access mode, i.e. by writing to the Indirect Segments Data Access register (ISDATA). This register allows to write up to 8 contiguous bits in a single write operation to the display memory:

  • SDATA[7:0], segments data value (see the figure above)
  • SDMASK[7:0], mask for SDATA. When SDMASK[y]=1, SDATA[y] is not written to display memory
  • OFF[5:0], byte offset in display memory (see the figure above)

Locking Shadow Display Memory

Shadow display memory can be locked so that it is not updated when new frames start.

Writing a '1' to the Lock bit in the Control B register (CTRLB.LOCK) will lock the shadow display memory. If the display memory is modified, the display remains unchanged.

Writing a '0' to CTRLB.LOCK will to unlock the shadow display memory. The shadow display memory will be updated when a new frame starts.