42.6.1.5 LCD Frame Frequency
The LCD frame frequency is defined as the number of times the segments are energized per second. The optimal frame frequency should be in range from 30Hz up to 100Hz to avoid flickering and ghosting effect.
The 32KHz oscillator clock (CLK_SLCD_OSC) is the base clock to define the LCD frame frequency (or frame rate) which in turn depends on the Duty Ratio bits in the Control A register (CTRLA.DUTY[2:0]). CLK_SLCD_OSC is used to generate the LCD waveform data for the enabled phases.
CLK_SLCD_OSC is first divided by a prescaler PVAL=16..128, then divided by DIV=1..8: The prescaler value PVAL is selected by writing the Prescaler bits in the Control A register (CTRLA.PRESC[1:0]), see table below.
| PRESC[1:0] | Prescaler Value (PVAL) |
|---|---|
| 0x0 | 16 |
| 0x1 | 32 |
| 0x2 | 64 |
| 0x3 | 128 |
The clock division factor DIV is selected by the Clock Divider bits CTRLA.CKDIV[2:0]. The division factor is DIV=CKDIV[2:0]+1. The duty ratio NB_COM is selected by writing to the Duty Ratio bits in the Control A register (CTRLA.DUTY).
The resulting frame rate is calculated according to this formula:
| Prescaler Value (PVAL) | CKDIV[2:0] | DIV | NB_COM | Frame Rate |
|---|---|---|---|---|
| 128 | 0x7 | 8 | 1 | 32 Hz |
| 128 | 0x2 | 3 | 1 | 85.3 Hz |
| 64 | 0x7 | 8 | 2 | 32 Hz |
| 64 | 0x2 | 3 | 2 | 85.3 Hz |
| 64 | 0x4 | 5 | 3 | 34.1 Hz |
| 32 | 0x3 | 4 | 3 | 85.3 Hz |
| 32 | 0x7 | 8 | 4 | 32 Hz |
| 32 | 0x2 | 3 | 4 | 85.3 Hz |
| 32 | 0x4 | 5 | 6 | 34.1 Hz |
| 16 | 0x3 | 4 | 6 | 85.3 Hz |
| 16 | 0x7 | 8 | 8 | 32 Hz |
| 16 | 0x2 | 3 | 8 | 85.3 Hz |