65.7.25 ADC Trigger Register

This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.

Name: ADC_TRGR
Offset: 0xC0
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 TRGPER[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 TRGPER[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      TRGMOD[2:0] 
Access R/WR/WR/W 
Reset 000 

Bits 31:16 – TRGPER[15:0] Trigger Period

Effective only if TRGMOD defines a periodic trigger.

Defines the periodic trigger period, with the following equation:

Trigger Period = (TRGPER + 1) / ADCCLK

The minimum time between two consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence depending on the configuration of registers ADC_MR, ADC_CHSR, ADC_SEQRx, ADC_TSMR.

When TRGMOD is set to pen detect trigger (i.e., 100) and averaging is used (i.e., field TSAV ≠ 0 in ADC_TSMR) only one measure is performed. Thus, XRDY, YRDY, PRDY, DRDY will not rise on pen contact trigger. To achieve measurement, several triggers must be provided either by software or by setting the TRGMOD on continuous trigger (i.e., 110) until flags rise.

Bits 2:0 – TRGMOD[2:0] Trigger Mode

ValueNameDescription
0 NO_TRIGGER No hardware trigger enabled, only software trigger can start conversions
1 EXT_TRIG_RISE Rising edge of the selected hardware trigger event, defined in ADC_MR.TRGSEL
2 EXT_TRIG_FALL Falling edge of the selected hardware trigger event
3 EXT_TRIG_ANY Any edge of the selected hardware trigger event
4 PEN_TRIG Pen Detect Trigger (shall be selected only if PENDET is set and TSMODE > 0)
5 PERIOD_TRIG ADC internal hardware periodic trigger (see field TRGPER)
6 CONTINUOUS Continuous mode