65.7.16 ADC Extended Mode Register

This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.

Name: ADC_EMR
Offset: 0x40
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
   ADCMODE[1:0] SIGNMODE[1:0]TAG 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 2322212019181716 
   SRCCLKASTE  OSR[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
   CMPFILTER[1:0]  CMPALL  
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
 CMPSEL[3:0] CMPTYPECMPMODE[1:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 29:28 – ADCMODE[1:0] ADC Running Mode

See 65.6.14 Automatic Error Correction for details on ADC running mode.

ValueNameDescription
0 NORMAL Normal mode of operation.
1 OFFSET_ERROR Offset Error mode to measure the offset error. See table ADC Running Modes.
2 GAIN_ERROR_HIGH Gain Error mode to measure the gain error. See table ADC Running Modes.
3 GAIN_ERROR_LOW Gain Error mode to measure the gain error. See table ADC Running Modes.

Bits 26:25 – SIGNMODE[1:0] Sign Mode

If conversion results are signed and resolution is below 16 bits, the sign is extended up to the bit 15 (for example, 0xF43 for 12-bit resolution will be read as 0xFF43 and 0x467 will be read as 0x0467). See 65.6.6 Conversion Results Format.

ValueNameDescription
0 SE_UNSG_DF_SIGN Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions.
1 SE_SIGN_DF_UNSG Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions.
2 ALL_UNSIGNED All channels: Unsigned conversions.
3 ALL_SIGNED All channels: Signed conversions.

Bit 24 – TAG Tag of ADC_LCDR

ValueDescription
0 Sets ADC_LCDR.CHNB field to zero.
1 Appends the channel number to the conversion result in ADC_LCDR.

Bit 21 – SRCCLK External Clock Selection

ValueNameDescription
0 PERIPH_CLK The peripheral clock is the source for the ADC prescaler.
1 GCLK GCLK is the source clock for the ADC prescaler, thus the ADC clock can be independent of the core/peripheral clock.

Bit 20 – ASTE Averaging on Single Trigger Event

ValueNameDescription
0 MULTI_TRIG_AVERAGE The average requests several trigger events.
1 SINGLE_TRIG_AVERAGE The average requests only one trigger event.

Bits 17:16 – OSR[1:0] Over Sampling Rate

ValueNameDescription
0 NO_AVERAGE No averaging. ADC sample rate is maximum.
1 OSR4 1-bit enhanced resolution by averaging. ADC sample rate divided by 4.
2 OSR16 2-bit enhanced resolution by averaging. ADC sample rate divided by 16.
3 OSR64 3-bit enhanced resolution by averaging. ADC sample rate divided by 64.
4 OSR256 4-bit enhanced resolution by averaging. ADC sample rate divided by 256.

Bits 13:12 – CMPFILTER[1:0] Compare Event Filtering

Number of consecutive compare events necessary to raise the flag = CMPFILTER+1

When programmed to 0, the flag rises as soon as an event occurs.

See 65.6.9 Comparison Window when using the filtering option (CMPFILTER > 0).

Bit 9 – CMPALL Compare All Channels

ValueDescription
0 Only channel indicated in CMPSEL field is compared.
1 All channels are compared.

Bits 7:4 – CMPSEL[3:0] Comparison Selected Channel

If CMPALL = 0: CMPSEL indicates which channel has to be compared.

If CMPALL = 1: No effect.

Bit 2 – CMPTYPE Comparison Type

ValueNameDescription
0 FLAG_ONLY Any conversion is performed and comparison function drives the ADC_ISR.COMPE flag.
1 START_CONDITION Comparison conditions must be met to start the storage of all conversions until the ADC_CR.CMPRST bit is set.

Bits 1:0 – CMPMODE[1:0] Comparison Mode

ValueNameDescription
0 LOW When the converted data is lower than the low threshold of the window, generates the ADC_ISR.COMPE flag. In Partial Wake-Up mode, defines the conditions to exit system from ULP1 mode.
1 HIGH When the converted data is higher than the high threshold of the window, generates the ADC_ISR.COMPE flag. In Partial Wake-Up mode, defines the conditions to exit system from ULP1 mode.
2 IN When the converted data is in the comparison window, generates the ADC_ISR.COMPE flag. In Partial Wake-Up mode, defines the conditions to exit system from ULP1 mode.
3 OUT When the converted data is out of the comparison window, generates the ADC_ISR.COMPE flag. In Partial Wake-Up mode, defines the conditions to exit system from ULP1 mode.