2 Bank Locations

RT PolarFire® SoC FPGA I/Os are grouped based on I/O voltage standards and I/O capabilities. Each I/O bank has dedicated I/O supplies and ground voltages. Because of these dedicated supplies, only I/O with compatible standards are assigned to the same I/O voltage bank.

The following illustrations show the bank locations for the RTPFS160ZT and RTPFS460ZT devices with available package combinations.
Important: This figure shows the top-view of the package. See the package orientation accordingly when interpreting pin positions or dimensions.
Figure 2-1. RTPFS460ZT-CG1509/FC1509/FCG1509 I/O Bank Locations
Important: This figure shows the top-view of the package. See the package orientation accordingly when interpreting pin positions or dimensions.
Figure 2-2. RTPFS160ZT-FCV784/FCVG784 I/O Bank Locations
Important: RTPFS160ZT in FCV784/FCVG784 is pin compatible with commercial part MPFS160T in FCVG784.
The following table lists the organization of the I/O banks in RT PolarFire SoC FPGAs. Each XCVR supports four lanes in every package. In all the packages, PCIe® is supported only in XCVR0.
Table 2-1. Organization of I/O Banks
Bank NumberFCV784/FCVG784CG1509/FC1509/FCG1509
RTPFS160ZTRTPFS460ZT
Bank 0HSIOHSIO
Bank 1GPIOGPIO
Bank 2MSSIOMSSIO
Bank 3JTAG/DEDIOJTAG/DEDIO
Bank 4MSSIOMSSIO
Bank 5 (MSS SGMII BANK)MSSIOMSSIO
Bank 6 (MSS DDR BANK)MSSIOMSSIO
Bank 7GPIOGPIO
Bank 8HSIOHSIO
Bank 9GPIOGPIO
XCVR 0IncludedIncluded
XCVR 1IncludedIncluded
XCVR 2—Included
XCVR 3—Included
XCVR 4—Included
XCVR 5—Included

Each I/O bank supports multiple DDR lanes. If CDR/SGMII interface is connected to the I/O bank, the Tx and Rx signal must be within the same DDR Lane. Only one CDR/SGMII is allowed per DDR lane. For more information about the DDR lanes for each package, see Package Pin Assignment Table (PPAT) and Product Family Product Overview.