11.4 SRAM Quality of Service
To ensure that hosts with latency requirements get sufficient priority when accessing RAM, priority levels can be assigned to the hosts for different types of access.
The Quality of Service (QoS) level is independently selected for each host accessing the RAM. For any access to the RAM, the RAM also receives a QoS level. The QoS levels and their corresponding bit values are shown in the following table.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |
Note: If a host is configured with QoS
level DISABLE (0x0) or LOW (0x1), there will be a minimum latency of one cycle to
get RAM access.
The priority order for concurrent accesses are decided by
two factors:
- As first priority, the QoS level for the host
- As a second priority, a static priority given by the port ID. The lowest port ID has the highest static priority.
| HS SRAM Port Connection | Port ID | Connection Type | QoS | default QoS |
|---|---|---|---|---|
| DMAC - Direct Memory Access Controller - Write-Back 1 Access | 6 | Direct | DMAC QOSCTRL.WRBQOS | 0x2 |
| DMAC - Direct Memory Access Controller - Write-Back 0 Access | 5 | Direct | DMAC QOSCTRL.WRBQOS | 0x2 |
| DMAC - Direct Memory Access Controller - Fetch 1 Access | 4 | Direct | DMAC QOSCTRL.FQOS | 0x2 |
| DMAC - Direct Memory Access Controller - Fetch 0 Access | 3 | Direct | DMAC QOSCTRL.FQOS | 0x2 |
| DMAC - Direct Memory Access Controller - Data Access | 2 | Bus Matrix | DMAC QOSCTRL.DQOS | 0x2 |
| DSU - Device Service Unit | 1 | Bus Matrix | DSU CFG.LQOS | 0x2 |
| CM23 - Cortex M23 Processor | 0 | Bus Matrix | 0x41008114, bits[1:0](1) | 0x3 |
Note:
- The CPU QoS level can be written/read, using 32-bit access only.