56 Revision History

Note: The data sheet revision is independent of the die revision (Revision bit in the Device Identification register of the Device Service Unit, DSU.DID.REVISION) and the device variant (last letter of the ordering number).

Revision J - 08/2023

This revision document is identical to the previous release.

Revision H - 06/2023

In addition to the changes listed in the following table, there were numerous typographical updates that were made throughout the document.

The following additions or updates were done during this revision:

Section Description
PAC
  • Updated access types in Overview
  • Updated the bitfield reset property for the DSU bitfield in the STATUSB Register
SUPC
RTC
DMAC
  • Added new content for Burst Transfer to DMA
PORT
SERCOM USART
  • Added in a new first paragraph for Data Transmission
  • Added a new note to the RXINV and TXINV bitfields for the CTRLA Register
TC
TRNG
ADC
AC
Electrical Characteristics at 85℃
Schematic Checklist

Revision G - 06/2021

In addition to the changes listed in the following table, there were numerous typographical updates that were made throughout the document.

Terminology in this document may not match with the contents of the current revision of the device errata or other Microchip documentation and collateral. If there are any questions or concerns regarding terminology, contact a Microchip support or sales representative.

The following additions or updates were done during this revision:

Section Description
General
  • Throughout the entire document all references of “Master” were changed to “Host,” and “Slave” was changed to “Client,” where applicable
  • Previous Revision histories were consolidated to clean up the flow of the document
Features Added new information for PWM Modes using TC peripherals.
Analog Peripherals Considerations Updated the note for Caution, and the Analog Signal Components Interconnections Diagram.
Memories
  • Updated Flash with a new Caution note
  • Updated Data Flash with a new Caution note
SAM L11 Specific Security Features
Clock System
MCLK
  • Updated Clock Ready Flag with text regarding the CPUDIV value
  • Updated the INTFLAG Register with new text for the CKRDY bitfield
FREQM
PM
  • Added all new text and a new caution note to SRAM Power Switch Configuration
  • Added a caution note to the PWCFG Register, and updated the existing KB Flash tables and added new tables for 32KB and 16KB
  • Corrected a typographical error in the INTFLAG Register
OSCCTRL
OSC32KCTRL
RTC Updated the following registers with new notes:
DMAC Updated the following registers with new bit alignment values:
PORT Updated the figure in the Functional Description
EVSYS
SERCOM Updated I/O Lines with new text
SERCOM USART
SERCOM SPI
  • Updated I/O Lines with new text
  • Updated the DOPO bitfield with new text in the CTRLA Register
SERCOM I2C
  • Updated I/O Lines with new text
  • Updated the CTRLB Register with new bitfield access values for the CMD and QCEN bitfields
TC
CCL Updated Truth Table Inputs Selection with a new figure for Linked Lut Input Selection
ADC
  • Removed non-applicable text from Events
  • Updated the SAMPLEN bitfield with new text and corrected the equation. A new note was added to refer to the ADC Electrical specifications.
  • Updated the table for the REFSEL bitfield in the REFCTRL Register for the value 0x1
AC Updated the Block Diagram to display DAC as DAC Output.
DAC
OPAMP Updated the Signal Description with a new note.
Schematic Checklist Updated the Introduction with all new content and a caution note for a noisy environment

Revision F - 06/2020

In addition to the changes listed in the following table, there were numerous typographical updates that were made throughout the document.

The following additions or updates were done during this revision:

Section Description
Features
Configuration Summary Added a new note to Table 1-1, SAM L10/L11 Device-Specific Features
Pinout
  • Moved the SERCOM related tables to the SERCOM Chapters
Memories
SAM L11 Specific Security Features
Boot ROM
DSU
MCLK Updated the offset for the CPUDIV register
FREQM Updated the Block Diagram and changed CLK_REF_MUX to CLK_REF
DMAC
  • Added new bit field description to the SRCADDR bit of the SRCADDR Register
  • Added new bit field description to the DSTADDR bit of the DSTADDR Register
NVMCTRL Updated the Silent Access section with new text and table
TRAM
SERCOM
SERCOM I2C Updated the Signal Description with a new note and Pinout tables
TC
  • Added new paragraph with information regarding the PER and PERBUF registers to Principle of Operation
  • Replaced the NPWM and NFRQ paragraph with new text in Waveform Output Operations
  • Updated the register property to PAC Write-Protection, Read-Synchronized, Write-Synchronized for the CTRLBSET register in 8-bit mode
  • Updated the bit description for the PER bit for the PER Register in 8-bit mode
  • Updated the bit description for the PER bit for the PER Register in 16-bit mode
  • Updated the bit description for the PER bit for the PER Register in 32-bit mode
TRNG Updated the DATA register with a new register property
ADC
OPAMP Added in a new topic, Reference Buffer (REFBUF)
Electrical Characteristics at 85℃
Electrical Characteristics at 125℃ Removed the last Equation in Analog-to-Digital Converter (ADC) Characteristics
AEC-Q100 Grade Electrical Characteristics

Revision E - 08/2019

The following additions or updates were done during this revision:

Section Description
Features Added the AEC-Q100 qualifications.
Multiplexed Signals Corrected typographical errors for note designations in the Pinout Multiplexing Table.
Peripherals Configuration Summary Corrected typographical errors in the table.
Electrical Specifications at 85°C
Electrical Specifications at 125°C
AEC-Q100 Electrical Specifications This section is newly added for this release.
50.2 Package Drawings 50.2.3 24-pin VQFN with Stepped Wettable Flanks (AEC-Q100 Grade 1) and 50.2.5 32-pin VQFN with Stepped Wettable Flanks (AEC-Q100 Grade 1)

Rev D - 04/2019

Section Updates
Features
Ordering Information
Memories
  • Created new TrustRAM topic
  • Updated NVM Software Calibration Row title from NVM Software Calibration Area. All references inside the topic have corrected the word ‘area’ to ‘row.’
Processor and Architecture
Peripherals Configuration Summary
SAM L11 Specific Security Features
  • Updated chapter title
  • Corrected typographical and minor content errors in Features
  • Updated Secure Pin Multiplexing on SERCOM with new content for feature enabling
  • Updated Data Flash Scrambling Chapter title from Data Flash, replaced the existing text with Data Flash scrambling information, and added a cross reference to the NVMCTRL.
Peripheral Access Controller
GCLK
MCLK
  • Updated the Peripheral Clock Default State table in Peripheral Clock Masking with new Peripheral Clock names:
    • CLK_APBA_AHB
    • CLK_APBB_AHB
    • CLK_APBC_AHB
    • CLK_HMATRIXHS_APB
FREQM
  • Updated the enable-protected references in the CTRLA register
PM
  • Updated the Register Property for the STDBYCFG Register to PAC Write-Protection
OSCCTRL
OSC32KCTRL
SUPC
WDT
RTC
DMAC
  • Corrected bit names in Events
  • The Not Enable-Protected attribute was updated for the CTRL register
  • The CHCTRLB register was updated to correct a bit offset
EIC
  • Changed the name of the EXTINTx bit in Events to EXTINT0-7
  • Updated the CTRLA Register with a new Register Property
  • Corrected a typographical error in the following registers changing Enabled-Protected to Enable-Protected:
NVMCTRL
TRAM
PORT - I/O Pin Controller
  • Updated the Cross Reference for the Nested Vector Interrupt Controller in Interrupts
  • Updated Register Access Protection with new introductory text and a reference to the INTFLAG register
  • Corrected typographical errors in Events
  • Added an Event Input Pin reference to the EVCTRL register
EVSYS
  • Added reference to the CHINTFLAGn register in Register Access Protection
  • Updated the register reset value on the READYUSR register
  • Corrected multiple bit names in the Event Generators table in the CHANNELn register
  • Corrected multiple values in the User Multiplexer Number m table of the USERm register
SERCOM
SERCOM - USART
  • Added new line item information for the CTRLC register and the RXPL register to Initialization
  • Updated the Register property for the CTRLA Register
SERCOM - SPI
  • Updated the Register properties and added “these bits are not synchronized” text to the following registers:
SERCOM I2C
  • Updated Register Access Protection to remove the reference to the ADDR Register
  • The Slave CTRLA Register was updated with a new Register property and the text “this bit is not synchronized” for the LOWTOUT bit
  • The Slave CTRLB Register has the register property corrected, and the text “These bits are not write synchronized,” removed
  • The Master CTRLA Register was updated with a new Register Property
TC
TRNG
CCL
  • Updated Events with new information, replacing OUTx with “LUT_n where n=0-1”
  • Updated the Enable bit of the LUTCTRL Register with new text, “This bit is not Enable-Protected”
ADC
  • Updated the name of the bus clock in Clocks to CLK_ADC_APB
  • SEQCTRLwas updated to remove an erroneous ‘n’ from the name of the Register.
AC
  • Updated Events to display the bit name COMP0-1, and removed information for START0 and START1
  • The following registers had their register properties updated:
DAC

Rev C - 02/2019

Section Updates
Configuration Summary Updated SAML10/L11 Family Features
Oscillators Pinout Updated XOSC32 Jitter Minimization
Memories
13.1  Features
Boot ROM
Device Service Unit (DSU) Updated STATUSB Register
Power Manager (PM)
Oscillators Controller (OSCCTRL)
32KHz Oscillators Controller (OSC32KCTRL) Updated the ULP32KSW bit in the OSCULP32K Register
Supply Controller (SUPC) Corrected erroneous text and added a note to Low Power VREF in Active Mode
Real Time Counter (RTC)
Direct Memory Access Controller (DMAC)
  • Updated the text for the DMAC Clocks section
  • Updated the LVLEN bits for the CRTL Register
  • Updated the LVLEX bits for the ACTIVE Register
External Interrupt Controller (EIC)
Nonvolatile Memory Controller (NVMCTRL)
TrustRAM (TRAM)
I/O Pin Controller (PORT)
Event System (EVSYS)
SERCOM USART
  • Updated the BAUD Register
  • Updated the equation in the RXPL Register
SERCOM I2C
  • Updated Signal Description
  • Updated the property for the slave DATA Register
  • Updated the master DATA Register
Timer/Counter (TC)
  • Updated the MCEO bits in the EVCTRL Register for 8-bit, 16-bit and 32-bit Modes
  • Updated The MC Bits in the INTENCLR, INTENSET, and INTFLAG Registers for 8-bit, 16-bit and 32-bit Modes
  • Updated the CCBUFV bit in the STATUS Register for 8-bit, 16-bit and 32-bit Modes
  • Updated the INVEN Bit in the DRVCTRL Register for 8-bit, 16-bit and 32-bit Modes
Configurable Custom Logic (CCL)
Analog-to-Digital Converter (ADC)
Analog Comparators (AC)
Digital-to-Analog Converter (DAC)
Operational Amplifier Controller (OPAMP)
Electrical Characteristics
Electrical Characteristics at 125°C
  • Updated “Operating Conditions Table” .
Schematic Checklist
  • Updated “External Analog Reference Schematic with one reference”.
Appendix A New Section for Migrating From SAM L21 to SAM L10/L11 (32-pin Package)
Appendix B New Section for Migrating From SAM D20/D21 to SAM L10/L11 (32-pin Package)

Rev B - 06/2018

Added new documentation for Electrical Characteristics -125°C.

Rev A - 09/2017

This is the initial released version of the document.