27.7.4.10 Counter Value in COUNT16 mode (CTRLA.MODE=1)
Note:
- This register is read-synchronized when CTRLA.COUNTSYNC = 1: SYNCBUSY.COUNT must be checked to ensure the COUNT register synchronization is complete.
- This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register synchronization is complete.
Name: | COUNT |
Offset: | 0x18 |
Reset: | 0x0000 |
Property: | PAC Write-Protection, Write-Synchronized |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
COUNT[15:8] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
COUNT[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |