31.6.2.1 Initialization

The following bits are enable-protected, meaning that they can only be written when the TRAM is disabled (CTRLA.ENABLE is zero):

• Tamper Erase bit in the Control A register (CTRLA.TAMPERS)
• Data Remanence Protection bit in the Control A register (CTRLA.DRP)
• Silent Access bit in the Control A register (CTRLA.SILACC)

The following registers are enable-protected:

• Data Scramble Control register (DSCC)

Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to one, but not at the same time as CTRLA.ENABLE is written to zero.

Enable-protection is denoted by the Enable-Protected property in the register description.