36.6.2.6.1 Host

In host mode (CTRLA.MODE=0x3), when Host SPI Enable Select (CTRLB.MSSEN) is ‘1’, hardware will control the SS line.

When Host SPI Select Enable (CTRLB.MSSEN) is '0', the SS line must be configured as an output. SS can be assigned to any general purpose I/O pin. When the SPI is ready for a data transaction, software must pull the SS line low.

When writing a character to the Data register (DATA), the character will be transferred to the shift register. Once the content of TxDATA has been transferred to the shift register, the Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) will be set. And a new character can be written to DATA.

Each time one character is shifted out from the host, another character will be shifted in from the client simultaneously. If the receiver is enabled (CTRLA.RXEN=1), the contents of the shift register will be transferred to the two-level or four-level receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in. And the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The received data can be retrieved by reading DATA.

When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. When the transaction is finished, the host must pull the SS line high to notify the client. If Host SPI Select Enable (CTRLB.MSSEN) is set to '0', the software must pull the SS line high.