37.2.4.4.2 Receive Buffer and FIFO Operation

The I3CxRXB register is safe to read when the contents of the register is full. This condition is represented through the Receive Buffer Full RXBF bit. This also sets the I3CxRXIF system level interrupt flag, which can also be used as a DMA trigger.
When the Target receives data from the Controller on the bus, it is received in the Receive FIFO. This data shifts through the Receiver FIFO and passes onto the I3CxRXB register, thus setting the RXBF and I3CxRXIF bits indicating that the Receive Buffer is full. Once the data are read by the user software, the RXBF and I3CxRXIF bits are cleared. Any available data in the Receive FIFO are then transferred to the I3CxRXB register, thus setting the RXBF/I3CxRXIF bits again. The RXBF and I3CxRXIF bits can also be cleared when a buffer reset operation has been performed using the CLRRXB bit. If the I3CxRXB Receive Buffer is read when it is empty (RXBF = 0), then a Receive Buffer Read Error occurs and the RXREIF interrupt flag is set. If the data being read from the I3CxRXB Receive Buffer are slower than the Controller’s writing speed, it is possible that the Receive FIFO will become full. If the Controller continues to write data to an already full Receive FIFO, a Receive Overrun occurs, and the RXOIF interrupt flag is set.
Table 37-9. Summary of Receive Status and Interrupt Flags
I3CxRXB Receive Buffer StatusReceive FIFO StatusRXBF/I3CxRXIFOther Interrupts
EmptyEmpty or Partially Full0RXREIF is set when read is attempted from the I3CxRXB register
EmptyFull0

RXREIF is set when read is attempted from the I3CxRXB register

RXOIF is set when write is attempted by the Controller(1)

FullFull1RXOIF is set when write is attempted by the Controller(1)
FullEmpty or Partially Full1
Note:
  1. The RXOIF Receive Overrun interrupt flag is set after every byte that the Controller writes to the Target when the Receive FIFO becomes full.
Important:
  1. While the Target will typically continue to receive data during a Private Write transaction as long as the Receive FIFO is not full, the receive operation can be limited if the Maximum Write Length (I3CxMWL register) is set. When the Maximum Write Length has been reached in a Private Write transaction, the Target will stop receiving further data and sets RXOIF Receive Overrun flag for every subsequent byte received thereafter, even if the Receive FIFO is not full. This does not affect the operation of the other Receive Status and Interrupt flags.
  2. This Target module will always ACK an I2C/Private Write request when the ACKP bit = 0, even if the Receive FIFO is full. To NACK an I2C/Private Write request, the ACKP bit must be set to 1. With ACKP bit set, a one-time ACK can be performed using the ACKPOS bit. Refer to Private Write Transaction for more information.